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intel ? celeron? processor datasheet product features the intel ? celeron? processor is designed for value pc desktops and is binary compatible with previous generation intel architecture processors. the intel ? celeron processor provides good performance for applications running on advanced operating systems such as windows* 95/98, windows* nt, and unix*. this is achieved by integrating the best attributes of intel processorsthe dynamic execution performance of the p6 microarchitecture plus the capabilities of mmx? technologybringing a balanced level of performance to the value pc market segment. the intel ? celeron processor offers the dependability you would expect from intel at an exceptional value. systems based on intel ? celeron processors also include the latest features to simplify system management and lower the cost of ownership for small business and home environments. n available at 500 mhz, 466 mhz, 433 mhz, 400 mhz, 366 mhz, 333 mhz, and 300a mhz core frequencies with 128 kb level-two cache; 300 mhz and 266 mhz core frequencies without level-two cache. n binary compatible with applications running on previous members of the intel microprocessor line. n dynamic execution microarchitecture. n operates on a 66 mhz, transaction-oriented system bus. n specifically designed for valued pc systems: based on the same p6 microarchitecture used in the pentium ? ii processor with the capabilities of mmx? technology. n power management capabilities. n optimized for 32-bit applications running on advanced 32-bit operating systems. n uses cost-effective packaging technology. single edge processor (s.e.p.) package to maintain compatibility with sc242 (processor core frequencies (mhz): 266, 300, 300a, 333, 366, 400, 433). plastic pin grid array (ppga) package (processor core frequencies (mhz): 300a, 333, 366, 400, 433, 466, 500). n integrated high performance 32 kb instruction and data, nonblocking, level- one cache: separate 16 kb instruction and 16 kb data caches. n integrated thermal diode. s.e.p. package ppga package order number: 243658-009 july 1999
datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructuions marked reserved or undefined. in tel reserves these for future definition and shall have no responsibility whatsoever for conflicts or imcompatibilities arising from future changes to them. the intel celeron? processor may contain design defects or errors known as errata which may cause the product to deviate from p ublished specifcations. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 1996, 1997, 1998, 1999. *third-party brands and names are the property of their respective owners.
datasheet 3 intel ? celeron? processor contents 1.0 introduction................................................................................................................ ......... 9 1.1 terminology .......................................................................................................... 9 1.1.1 package terminology.............................................................................10 1.2 references ..........................................................................................................10 2.0 electrical specifications................................................................................................... .12 2.1 the intel ? celeron? processor system bus and v ref ......................................12 2.2 clock control and low power states..................................................................12 2.2.1 normal statestate 1 ...........................................................................12 2.2.2 autohalt power down statestate 2 .................................................13 2.2.3 stop-grant statestate 3 .....................................................................13 2.2.4 halt/grant snoop statestate 4 ........................................................14 2.2.5 sleep statestate 5..............................................................................14 2.2.6 deep sleep statestate 6 ....................................................................15 2.2.7 clock control..........................................................................................15 2.3 intel ? celeron? processor power and ground pins ..........................................15 2.4 intel ? celeron? processor decoupling ..............................................................16 2.4.1 intel ? celeron? processor system bus agtl+ decoupling.................16 2.5 voltage identification ...........................................................................................16 2.6 intel ? celeron? processor system bus unused pins........................................17 2.7 intel ? celeron? processor system bus signal groups .....................................18 2.7.1 asynchronous vs. synchronous for system bus signals ......................19 2.7.2 system bus frequency select signal (bsel)........................................19 2.8 test access port (tap) connection....................................................................19 2.9 maximum ratings................................................................................................20 2.10 processor dc specifications...............................................................................20 2.11 agtl+ system bus specifications .....................................................................23 2.12 intel ? celeron? processor system bus ac specifications................................24 3.0 system bus signal simulations........................................................................................36 3.1 intel ? celeron? processor system bus clock (bclk) signal quality specifications and measurement guidelines ......................................................36 3.2 agtl+ signal quality specifications and measurement guidelines ..................38 3.3 non-agtl+ signal quality specifications and measurement guidelines...........40 3.3.1 overshoot/undershoot guidelines .........................................................40 3.3.2 ringback specification ...........................................................................41 3.3.3 settling limit guideline...........................................................................41 4.0 thermal specifications and design considerations.........................................................42 4.1 thermal specifications ........................................................................................42 4.1.1 thermal diode........................................................................................43 4.2 thermal parameters............................................................................................43 4.2.1 ambient temperature.............................................................................43 4.2.2 thermal resistance ...............................................................................43 4.2.3 thermal solution performance...............................................................44 4.3 thermal solution attach methods .......................................................................44
intel ? celeron? processor 4 datasheet 5.0 mechanical specifications................................................................................................ 45 5.1 s.e.p. package ................................................................................................... 45 5.1.1 materials information.............................................................................. 45 5.1.2 signal listing ......................................................................................... 46 5.2 ppga package ................................................................................................... 55 5.2.1 materials information.............................................................................. 55 5.2.2 signal listing.......................................................................................... 57 5.3 heat sink volumetric keepout zone guidelines ................................................. 68 6.0 boxed processor specifications....................................................................................... 68 6.1 s.e.p. package ................................................................................................... 68 6.1.1 introduction ............................................................................................ 68 6.1.2 mechanical specifications ...................................................................... 69 6.1.2.1 boxed processor heat sink dimensions................................... 70 6.1.2.2 boxed processor heat sink weight .......................................... 71 6.1.2.3 boxed processor retention mechanism ................................... 71 6.1.3 boxed processor requirements............................................................. 71 6.1.4 thermal specifications ........................................................................... 72 6.1.4.1 boxed processor cooling requirements .................................. 72 6.2 ppga package ................................................................................................... 73 6.2.1 introduction ............................................................................................ 73 6.2.2 mechanical specifications ...................................................................... 73 6.2.2.1 boxed processor heat sink dimensions................................... 75 6.2.2.2 boxed processor heat sink weight .......................................... 75 6.2.2.3 boxed processor thermal cooling solution clip ...................... 76 6.2.3 boxed processor requirements............................................................. 76 6.2.4 thermal specifications ........................................................................... 78 6.2.4.1 boxed processor cooling requirements .................................. 78 7.0 intel ? celeron? processor signal description ................................................................ 79 7.1 signal summaries ............................................................................................... 85
datasheet 5 intel ? celeron? processor figures 1 clock control state machine...............................................................................13 2 bclk to core logic offset ..................................................................................33 3 bclk*, picclk, and tck generic clock waveform .........................................33 4intel ? celeron? processor system bus valid delay timings ............................34 5intel ? celeron? processor system bus setup and hold timings......................34 6intel ? celeron? processor system bus reset and configuration timings........34 7 power-on reset and configuration timings.......................................................35 8 test timings (tap connection) ..........................................................................35 9 test reset timings .............................................................................................35 10 bclk, tck, picclk generic clock waveform at the processor core pins .....37 11 bclk, tck, picclk generic clock waveform at the processor edge fingers ................................................................................................................38 12 low to high agtl+ receiver ringback tolerance.............................................39 13 non-agtl+ overshoot/undershoot, settling limit, and ringback .....................40 14 intel ? celeron? processor substrate dimensions (s.e.p. package) ................46 15 intel ? celeron? processor substrate primary/secondary side dimensions (s.e.p. package) .............................................................................46 16 ppga package dimensions................................................................................55 17 ppga package (pin side view)..........................................................................57 18 boxed intel ? celeron? processor in s.e.p. package in the retention mechanism..........................................................................................69 19 side view space requirements for the boxed processor ..................................69 20 front view space requirements for the boxed processor .................................70 21 top view airspace requirements for the boxed processor ...............................70 22 boxed processor fan heat sink power cable connector description ...............71 23 motherboard power header placement relative to fan power connector and sc242.........................................................................................72 24 boxed intel ? celeron? processor in ppga package ........................................73 25 side view space requirements for the boxed processor ..................................74 26 top view space requirements for the boxed processor ...................................74 27 side view airspace requirements for the boxed processor ..............................75 28 boxed processor fan heat sink power cable connector description ...............76 29 motherboard power header placement relative to the intel ? celeron? processor in the ppga package .............................................77 30 top view of motherboard keepout requirements ..............................................77 31 side view of motherboard keepout requirements .............................................78
intel ? celeron? processor 6 datasheet tables 1 voltage identification definition .......................................................................... 17 2 intel ? celeron? processor system bus signal groups ..................................... 18 3 intel ? celeron? processor absolute maximum ratings .................................... 20 4 intel ? celeron? processor voltage and current specifications ....................... 21 5 agtl+ signal groups dc specifications ........................................................... 23 6 non-agtl+ signal group dc specifications ..................................................... 23 7 intel ? celeron? processor agtl+ bus specifications ..................................... 24 8 intel ? celeron? processor system bus ac specifications (clock) at the processor edge fingers for the s.e.p. package ..................................... 25 9 intel ? celeron? processor system bus ac specifications (clock) at the processor core pins for both s.e.p. and ppga packages ............................. 26 10 valid intel ? celeron? processor system bus, core frequency ....................... 26 11 intel ? celeron? processor system bus ac specifications (agtl+ signal group) at the processor edge fingers for the s.e.p. package ............. 27 12 intel ? celeron? processor system bus ac specifications (agtl+ signal group) at the processor core pins for the s.e.p. package .................. 27 13 processor system bus ac specifications (agtl+ signal group) at the processor core pins for the ppga package ..................................................... 28 14 intel ? celeron? processor system bus ac specifications (cmos signal group) at the processor edge fingers for s.e.p. package ................... 28 15 intel ? celeron? processor system bus ac specifications (cmos signal group) at the processor core pins for both s.e.p. and ppga packages ....... 29 16 intel ? celeron? processor system bus ac specifications (reset conditions) 29 17 intel ? celeron? processor system bus ac specifications (apic clock and apic i/o) at the processor edge fingers for s.e.p. package .......................... 30 18 intel ? celeron? processor system bus ac specifications (apic clock and apic i/o) at the processor core pins for s.e.p. and ppga packages .... 30 19 intel ? celeron? processor system bus ac specifications (tap connection) at the processor edge fingers for s.e.p. package .......................................... 31 20 intel ? celeron? processor system bus ac specifications (tap connection) at the processor core pins for both s.e.p. and ppga packages ................... 32 21 bclk signal quality specifications for simulation at the processor core for both s.e.p. and ppga packages ............................................................... 36 22 bclk signal quality guidelines for edge finger measurement on the s.e.p. package .................................................................................................. 37 23 agtl+ signal groups ringback tolerance specifications at the processor core for both the s.e.p. and ppga packages ................................................. 38 24 agtl+ signal groups ringback tolerance guidelines for edge finger measurement on the s.e.p. package ................................................................. 39 25 signal ringback specifications for non-agtl+ signal simulation at the processor core for both s.e.p. and ppga packages ..................................... 41 26 signal ringback guidelines for non-agtl+ signal edge finger measurement on the s.e.p. package ................................................................ 41 27 intel ? celeron? processor power for the s.e.p. package ............................... 42 28 intel ? celeron? processor power for the ppga package ................................ 42 29 thermal diode parameters ................................................................................. 43 30 thermal diode interface...................................................................................... 43 31 example thermal solution performance for 266 mhz intel ? celeron? processor at power of 16.6 watts............................................ 44 32 s.e.p. package signal listing by pin number.................................................... 47
datasheet 7 intel ? celeron? processor 33 s.e.p. package signal listing by signal name .................................................51 34 ppga package dimensions................................................................................56 35 ppga package information summary ................................................................56 36 ppga package signal listing by pin number ....................................................58 37 ppga package signal listing in order by signal name.....................................63 38 boxed processor fan heat sink spatial dimensions .........................................70 39 fan heat sink power and signal specifications .................................................72 40 boxed processor fan heat sink spatial dimensions ........................................75 41 fan heat sink power and signal specifications .................................................76 42 alphabetical signal reference ............................................................................79 43 output signals.....................................................................................................85 44 input signals........................................................................................................85 45 input/output signals (single driver)....................................................................86 46 input/output signals (multiple driver) .................................................................86
intel ? celeron? processor 8 datasheet
datasheet 9 intel ? celeron? processor 1.0 introduction the intel ? celeron? p r ocessor is based on the p6 microarchitecture and i s optimized for the v alue pc market segmen t . the intel celeron processo r , like th e pen t ium ? ii processo r , features a dynamic execution microarchitectu r e and executes mmx technology instructions fo r enhanced media a nd communication performance . the intel celeron processor also utilizes multiple low- po w e r states such as autoha l t , stop-grant , sleep, and deep sleep to conserve powe r during idl e times. the i n tel cele r on p r ocesso r is capable of r u nni n g t o da y s most c o mmo n pc a p plicati o ns with u p to 4 gb of cacheabl e memory space. as this processor is intended for v a lue pc systems, it does not provid e multiprocessor support. the pentium ii an d pentium ? ii i processo r s should be used f or multiprocessor sys t em designs. t o be cost-e f fective at both the processor and system l evel, t h e intel celeron processor u t ilizes two cost-e f fective packaging technologies. t hey a r e the s.e. p . (single- e dge processo r ) packag e and ppga (plastic pin g rid array) package. refer to th e intel ? cele r on? p r ocessor specification upd a te fo r the latest packa g ing a nd f req u enc y s u pp o rt inf o rmatio n (or d er num b er 2 43 3 37). note: this datasheet describes the i nte l cele r o n processo r fo r both the ppga package an d the s.e. p . package versions . u nless otherwise specif i ed, the informat i on in this document applies to bo t h ver s io n s. 1.1 t erminology in this document, a # symbol after a signal name refers to an active low signal. this mean s tha t a signal is in the active state (based on the name of the signal) when driven to a low level. for example, when f l ush # is lo w , a flush has been requested. when nm i is high, a nonmaskable interrupt has occurred. in th e case of signals wher e the name does not imply an activ e state but describes pa r t of a binary sequence ( such as ad d r ess or dat a ), the # symbol implies t hat the s i gnal is inv e rted. for example , d[3:0] = hlh l r efers to a hex a , and d# [ 3:0] = lhlh also re f ers to a hex a (h= high logic level , l= low logic level). th e term system bus refers to the interfac e between th e processo r , system core logic (a.k.a . the agpset components), and other bus agents. th e system bus is an interface to th e processo r , memor y , and i/o.
10 datasheet intel ? celeron? processor 1.1.1 package terminology the following terms are used often in this document and are explained here for clarification: ? processor substrate the structure on which passive components (resistors and capacitors) are mounted. ? processor core the processors execution engine. ? s.e.p. package single-edge processor package, which consists of a processor substrate, processor core, and passive components. this package differs from the s.e.c. cartridge as this processor has no external plastic cover, thermal plate, or latch arms. ? ppga package plastic pin grid array package. the package is a pinned laminated printed circuit board structure. additional terms referred to in this and other related documentation: ? sc242 242-contact slot connector. a processor in the s.e.p. package uses this connector to interface with a system board. ? 370-pin socket (pga370) the zero insertion force (zif) socket in which a processor in the ppga package will use to interface with a system board. ? retention mechanism a mechanical assembly which holds the package in the sc242 connector. 1.2 references 1,2 the reader of this specification should also be familiar with material and concepts presented in the following documents: ? intel ? celeron? processor support component suppliers (http://developer.intel.com/design/celeron/componets/) ? ap-485, intel processor identification and the cpuid instruction (order number 241618) ? ap-585, pentium ? ii processor agtl+ guidelines (order number 243330) ? ap-586, pentium ? ii processor thermal design guidelines (order number 243331) ? ap-587, pentium ? ii processor power distribution guidelines (order number 243332) ? ap-589, design for emi (order number 243334) ? pentium ? ii processor at 233, 266, 300, and 333 mhz datasheet (order number 243335) ? pentium ? ii processor at 350, 400, and 450 mhz datasheet (order number 243657) ? intel ? celeron? processor specification update (order number 243337) ? sc242 connector design guidelines (order number 243397) ? pentium ? ii processor developers manual (order number 243502) ? 370-pin socket (pga370) design guidelines (order number 244410) ? intel architecture software developer's manual (order number 243193) volume i: basic architecture (order number 243190) volume ii: instruction set reference (order number 243191) volume iii: system programming guide (order number 243192)
datasheet 11 intel ? celeron? processor ? pentium ? ii processor i/o buffer models , quad xtk format (electronic form) ? intel ? 440ex agpset design guide (order number 290637) ? intel ? celeron? processor with the intel ? 440lx agpset design guide (order number 245088) ? intel ? 440bx agpset design guide (order number 290634) ? intel ? celeron? processor with the intel ? 440zx-66 agpset design guide (order number 245126) ? intel ? celeron? processor (ppga) at 466 mhz thermal solutions guidelines (order number 245156) notes: 1. this reference material can be found on the intel developers website located at: http://developer.intel.com 2. for a complete listing of the intel ? celeron? processor reference material, refer to the intel developers website when this processor is formally launched. the website is located at: http://developer.intel.com/design/celeron/
12 datasheet intel ? celeron? processor 2.0 electrical specifications 2.1 the intel ? celeron? processor system bus and v ref intel ? celeron processor signals use a variation of the low voltage gunning transceiver logic (gtl) signaling technology. the intel celeron processor system bus specification is similar to the gtl specification, but has been enhanced to provide larger noise margins and reduced ringing. the improvements are accomplished by increasing the termination voltage level and controlling the edge rates. because this specification is different from the standard gtl specification, it is referred to as assisted gunning transceiver logic (agtl+) in this document. the intel ? celeron processor varies from the pentium pro processor in its output buffer implementation. the buffers that drive the system bus signals on the intel ? celeron processor are actively driven to v cc core for one clock cycle during the low-to-high transition. this improves rise times and reduces overshoot. these signals should still be considered open-drain and require termination to a supply that provides the logic-high signal level. the agtl+ inputs use differential receivers which require a reference signal (v ref ). v ref is used by the receivers to determine if a signal is a logic-high or a logic-low, and is provided to the processor core by either the processor substrate (s.e.p. package) or the motherboard (ppga package). local v ref copies should be generated on the motherboard for all other devices on the agtl+ system bus. termination is used to pull the bus up to the high voltage level and to control reflections on the transmission line. the processor may contain termination resistors (s.e.p. package only) that provide termination for one end of the intel celeron processor system bus. otherwise, this termination must exist on the motherboard. the agtl+ bus depends on incident wave switching. therefore timing calculations for agtl+ signals are based on motherboard flight time as opposed to capacitive deratings. analog signal simulation of the intel celeron processor system bus, including trace lengths, is highly recommended when designing a system. see the pentium ? ii processor agtl+ layout guidelines and the pentium ? ii processor i/o buffer models, quad format (electronic form) for details. 2.2 clock control and low power states intel ? celeron processors allow the use of autohalt, stop-grant, sleep, and deep sleep states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. see figure 1 for a visual representation of the intel celeron processor low power states. for the processor to fully realize the low current consumption of the stop-grant, sleep, and deep sleep states, a model specific register (msr) bit must be set. for the msr at 02ah (hex), bit 26 must be set to a 1 (this is the power on default setting) for the processor to stop all internal clocks during these modes. for more information, see the pentium ? ii processor developer's manual (order number 243502). 2.2.1 normal statestate 1 this is the normal operating state for the processor.
datasheet 13 intel ? celeron? processor 2.2.2 autohalt power down statestate 2 autohalt is a low power state entered when the processor executes the halt instruction. the processor will transition to the normal state upon the occurrence of smi#, binit#, init#, or lint[1:0] (nmi, intr). reset# will cause the processor to immediately initialize itself. the return from a system management interrupt (smi) handler can be to either normal mode or the autohalt power down state. see the intel architecture software developer's manual, volume iii: system programmer's guide (order number 243192) for more information. flush# will be serviced during the autohalt state, and the processor will return to the autohalt state. the system can generate a stpclk# while the processor is in the autohalt power down state. when the system deasserts the stpclk# interrupt, the processor will return execution to the halt state. 2.2.3 stop-grant statestate 3 the stop-grant state on the processor is entered when the stpclk# signal is asserted. figure 1. clock control state machine 2. auto halt power down state bclk running. snoops and interrupts allowed. halt instruction and halt bus cycle generated init#, binit#, intr, smi#, reset# 1. normal state normal execution. stpclk# asserted stpclk# de-asserted 3. stop grant state bclk running. snoops and interrupts allowed. slp# asserted slp# de-asserted 5. sleep state bclk running. no snoops or interrupts allowed. bclk input stopped bclk input restarted 6. deep sleep state bclk stopped. no snoops or interrupts allowed. 4. halt/grant snoop state bclk running. service snoops to caches. snoop event occurs snoop event serviced snoop event occurs snoop event serviced stpclk# asserted stpclk# de-asserted
14 datasheet intel ? celeron? processor since the agtl+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to v tt ) for minimum power drawn by the termination resistors in this state. in addition, all other input pins on the system bus should be driven to the inactive state. binit# will not be serviced while the processor is in stop-grant state. the event will be latched and can be serviced by software upon exit from stop-grant state. flush# will not be serviced during stop-grant state. reset# will cause the processor to immediately initialize itself, but the processor will stay in stop-grant state. a transition back to the normal state will occur with the deassertion of the stpclk# signal. a transition to the halt/grant snoop state will occur when the processor detects a snoop on the system bus (see section 2.2.4 ). a transition to the sleep state (see section 2.2.4 ) will occur with the assertion of the slp# signal. while in the stop-grant state, smi#, init#, and lint[1:0] will be latched by the processor, and only serviced when the processor returns to the normal state. only one occurrence of each event will be recognized upon return to the normal state. 2.2.4 halt/grant snoop statestate 4 the processor will respond to snoop transactions on the intel ? celeron processor system bus while in stop-grant state or in autohalt power down state. during a snoop transaction, the processor enters the halt/grant snoop state. the processor will stay in this state until the snoop on the intel celeron processor system bus has been serviced (whether by the processor or another agent on the intel celeron processor system bus). after the snoop is serviced, the processor will return to the stop-grant state or autohalt power down state, as appropriate. 2.2.5 sleep statestate 5 the sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (pll), and has stopped all internal clocks. the sleep state can only be entered from stop-grant state. once in the stop-grant state, the slp# pin can be asserted, causing the processor to enter the sleep state. the slp# pin is not recognized in the normal or autohalt states. snoop events that occur while in sleep state or during a transition into or out of sleep state will cause unpredictable behavior. in the sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals (with the exception of slp# or reset#) are allowed on the system bus while the processor is in sleep state. any transition on an input signal before the processor has returned to stop-grant state will result in unpredictable behavior. if reset# is driven active while the processor is in the sleep state, and held active as specified in the reset# pin specification, then the processor will reset itself, ignoring the transition through stop-grant state. if reset# is driven active while the processor is in the sleep state, the slp# and stpclk# signals should be deasserted immediately after reset# is asserted to ensure the processor correctly executes the reset sequence.
datasheet 15 intel ? celeron? processor while in the sleep state, the processor is capable of entering its lowest power state, the deep sleep state, by stopping the bclk input. (see section 2.2.6 .) once in the sleep state, the slp# pin can be deasserted if another asynchronous system bus event occurs. the slp# pin has a minimum assertion of one bclk period. 2.2.6 deep sleep statestate 6 the deep sleep state is the lowest power state the processor can enter while maintaining context. the deep sleep state is entered by stopping the bclk input (after the sleep state was entered from the assertion of the slp# pin). the processor is in deep sleep state immediately after blck is stopped. it is recommended that the blck input be held low during the deep sleep state. stopping of the bclk input lowers the overall current consumption to leakage levels. to re-enter the sleep state, the blck input must be restarted. a period of 1 ms (to allow for pll stabilization) must occur before the processor can be considered to be in the sleep state. once in the sleep state, the slp# pin can be deasserted to re-enter the stop-grant state. while in deep sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals are allowed on the system bus while the processor is in deep sleep state. any transition on an input signal before the processor has returned to stop-grant state will result in unpredictable behavior. 2.2.7 clock control when the processor is in the sleep or deep sleep states, it will not respond to interrupts or snoop transactions. picclk should not be removed during the autohalt power down or stop-grant states. picclk can be removed during the sleep or deep sleep states. when transitioning from the deep sleep state to the sleep state, picclk must be restarted with bclk. 2.3 intel ? celeron? processor power and ground pins there are five pins defined on the s.e.p. package for voltage identification (vid) and there are four pins on the ppga package. these pins specify the voltage required by the processor core. these have been added to cleanly support voltage specification variations on current and future intel ? celeron processors. for clean on-chip power distribution, intel celeron processors in the s.e.p. package have 27 v cc (power) and 30 v ss (ground) inputs. the 27 v cc pins are further divided to provide the different voltage levels to the components. v cc core inputs for the processor core account for 19 of the v cc pins, while 4 v tt inputs (1.5 v) are used to provide a agtl+ termination voltage to the processor. for only the s.e.p. package, one v cc 5 pin is provided for voltage transient tools. v cc 5 and v cc core must remain electrically separated from each other. the ppga package has more power (88) and ground (80) pins than the s.e.p. package. of the power pins, 77 are used for the processor core (v cc core ) and 8 are used as a agtl+ reference voltage (v ref ). the other 3 power pins are v cc 1.5 , v cc 2.5 and v cc cmos and are used for future processor compatibility. the v cc cmos pin is provided as a feature for future processor support in a flexible design. in such a design, the v cc cmos pin is used to provide the cmos voltage for use by the platform. additionally, 2.5 v must be provided to the v cc 2.5 input and 1.5 v must be provided to the v cc 1.5 input. the processor routes the cmos voltage level through the package that it is compatible with. for example, future processors requiring 1.5 v cmos voltage levels route 1.5 v to the v cc cmos output.
16 datasheet intel ? celeron? processor each power signal, regardless of package, must meet the specifications stated in table 4. in addition, all v cc core pins must be connected to a voltage island while all v ss pins have to connect to a system ground plane. 2.4 intel ? celeron? processor decoupling due to the large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. this causes voltages on power planes to sag below their nominal values if bulk decoupling is not adequate. care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in table 4 . failure to do so can result in timing violations or a reduced lifetime of the component. 2.4.1 intel ? celeron? processor system bus agtl+ decoupling the s.e.p. package contains high frequency decoupling capacitance on the processor substrate, where the ppga package does not. therefore, intel ? celeron? processors in the ppga package require high frequency decoupling on the system motherboard. bulk decoupling must be provided on the motherboard for proper agtl+ bus operation for both packages. see ap-585, pentium ? ii processor agtl+ guidelines (order number 243330), ap-587, pentium ? ii processor power distribution guidelines (order number 243332), and the pentium ? ii processor developer's manual (order number 243502) for more information. 2.5 voltage identification the processors voltage identification (vid) pins can be used to automatically select the v cc core voltage from a compatible voltage regulator. there are five vid pins (vid[4:0]) on the s.e.p. package, while there are only four (vid[3:0]) on the ppga package. this is because there are no intel ? celeron? processors in the ppga package that require more than 2.05 v (see table 1). vid pins are not signals, but rather are an open or short circuit to v ss on the processor. the combination of opens and shorts defines the processor cores required voltage. the vid pins also allow for compatibility with current and future intel celeron processors. note that the 11111 (all opens) id can be used to detect the absence of a processor core in a given slot (s.e.p. package only), as long as the power supply used does not affect the vid signals. detection logic and pull-ups should not affect vid inputs at the power source (see section 7.0). external logic monitoring the vid signals or the voltage regulator may require the vid pins to be pulled-up. if this is the case, the vid pins should be pulled up to a ttl-compatible level with external resistors to the power source of the regulator. the power source chosen must be guaranteed to be stable whenever the voltage regulators supply is stable. this will prevent the possibility of the processor supply going above the specified v cc core in the event of a failure in the supply for the vid lines. in the case of a dc-to-dc converter, this can be accomplished by using the input voltage to the converter for the vid line pull-ups. in addition, the power supply must supply the requested voltage or disable itself.
datasheet 17 intel ? celeron? processor , notes: 1. 0 = processor pin connected to v ss . 2. 1 = open on processor; may be pulled up to ttl v ih on motherboard. 3. the intel ? celeron? processor core will be powered off 2.0 v. 4. vid4 applies only to the s.e.p. package. vid[3:0] applies to both s.e.p. and ppga packages. 5. for ppga, only the shaded area applies. 2.6 intel ? celeron? processor system bus unused pins all reserved p ins must remain unconnected. connection of these p ins to v cc core , v ss , or to an y other si g nal (includin g each other) can result in com p onent malfunction or incom p atibilit y with future intel ? celeron? p rocessor p roducts. see section 5.0 for a p in listin g of the p rocessor and the location of each reserved p in. for intel celeron p rocessors in the s.e.p. packa g e, the testhi p in must be at a lo g ic-hi g h level when the core p ower su pp l y comes u p . for more information, p lease refer to erratum c26 of the intel ? celeron? processor specification update (order number 243748). also note that the testhi si g nal is not available on intel celeron p rocessors in the ppga p acka g e. picclk must be driven with a valid clock in p ut and the picd[1:0] lines must be p ulled-u p to 2.5 v even when the apic will not be used. a se p arate p ull-u p resistor must be p rovided for each picd line. for reliable o p eration, alwa y s connect unused in p uts or bi-directional si g nals to their deasserted si g nal level. the p ull-u p or p ull-down resistor value is s y stem de p endent and should be chosen such that the lo g ic-hi g h (v ih ) and lo g ic-low (v il ) re q uirements are met. for the s.e.p. packa g e, unused agtl+ in p uts should not be connected as the p acka g e substrate has termination resistors. on the other hand, ppga does not have agtl+ termination in its p acka g e and must have an y unused agtl+ in p uts terminated throu g h a p ull-u p resistor. for unused cmos in p uts, active-low si g nals should be connected throu g h a p ull-u p resistor to meet v ih re q uirements and active-hi g h si g nals should be connected throu g h a p ull-down resistor to meet v il re q uirements. unused cmos out p uts can be left unconnected. a resistor must be used when t y in g bi-directional si g nals to p ower or g round. for an y si g nal p ulled to either p ower or g round, a resistor will allow for s y stem testabilit y . table 1. voltage identification definition 1, 2, 3, 5 processor pins vid4 (s.e.p.p. only) vid3 vid2 vid1 vid0 v cc core 0 0 0 1 1 1.90 0 0 0 1 0 1.95 0 0 0 0 1 2.00 3 0 0 0 0 0 2.05 1 1111 no core 1 1110 2.1
18 datasheet intel ? celeron? processor 2.7 intel ? celeron? processor system bus signal groups to simplify the following discussion, the intel ? celeron? processor system bus signals have been combined into groups by buffer type. all intel ? celeron? processor system bus outputs are open drain and require a high-level source provided externally by the termination or pull-up resistor. agtl+ input signals have differential input buffers, which use v ref as a reference signal. agtl+ output signals require termination to 1.5 v. in this document, the term "agtl+ input" refers to the agtl+ input group as well as the agtl+ i/o group when receiving. similarly, "agtl+ output" refers to the agtl+ output group as well as the agtl+ i/o group when driving. emi pins (s.e.p. package only) should be connected to motherboard ground and/or to chassis ground through zero ohm (0 w ) resistors. the zero ohm resistors should be placed in close proximity to the sc242 connector. the path to chassis ground should be short in length and have a low impedance. the cmos, clock, apic, and tap inputs can each be driven from ground to 2.5 v. the cmos, apic, and tap outputs are open drain and should be pulled high to 2.5 v. this ensures not only correct operation for current intel celeron processors, but compatibility for future intel celeron processor products as well. the groups and the signals contained within each group are shown in table 2 . refer to section 7.0 for descriptions of these signals. notes: 1. see section 7.0 for information on the pwrgood signal. 2. see section 7.0 for information on the slp# signal. 3. see section 7.0 for information on the thermtrip# signal. 4. these signals are specified for 2.5 v operation. table 2. intel ? celeron? processor system bus signal groups group name signals agtl+ input bpri#, defer#, reset#, rs[2:0]#, trdy# agtl+ output prdy# agtl+ i/o a[31:3]#, ads#, bnr#, bp[3:2]#, bpm[1:0]#, br0#, d[63:0]#, dbsy#, drdy#, hit#, hitm#, lock#, req[4:0]#, cmos input 4 a20m#, flush#, ignne#, init#, lint0/intr, lint1/nmi, preq#, pwrgood 1 , smi#, slp# 2 , stpclk# cmos output 4 ferr#, ierr#, thermtrip# 3 system bus clock bclk apic clock picclk apic i/o 4 picd[1:0] tap input 4 tck, tdi, tms, trst# tap output 4 tdo power/other 5 bsel, cpupres# 7 , edgtrl 7 , emi 6 , pll[2:1] 7 , slotocc# 6 , thermdp, thermdn, v cc 1.5 7 , v cc 2.5 7 , v cc l2 5 , v cc 5 6 , v cc cmos 7 , v cc core , v core det 7 , vid[3:0] 7 , vid[4:0] 6 , v ref [7:0] 7 , v ss , v tt 6
datasheet 19 intel ? celeron? processor 5. v cc core is the power supply for the processor core. vid[4:0] and vid[3:0] are described in section 2.0 . v tt is used to terminate the system bus and generate v ref on the processor substrate. v ss is system ground. v cc 5 is not connected to the intel ? celeron? processor. this supply is used for voltage transient tools. slotocc# is described in section 7.0 . bsel is described in section 2.7.2 and section 7.0 . emi pins are described in section 7.0 . v cc l2 is a pentium ? ii processor reserved signal provided to maintain compatibility with the pentium ? ii processor and may be left as a no-connect for intel celeron processor-only designs. 6. only applies to intel celeron processors in the s.e.p. package. 7. only applies to intel celeron processors in the ppga package. 2.7.1 asynchronous vs. synchronous for system bus signals all agtl+ signals are synchronous to bclk. all of the cmos, apic, and tap signals can be applied asynchronously to bclk. all apic signals are synchronous to picclk. all tap signals are synchronous to tck. 2.7.2 system bus frequency select signal (bsel) the bsel pin has two functions. first, it acts as an output and can be used by an external clock generator to select the proper system bus frequency. second, it acts as an input and can be used by a system bios to detect and report the processor core frequency. please see the intel ? celeron? processor with the intel ? 440zx-66 agpset design guide (order number 245126) for an example implementation of bsel. bsel is 3.3 v tolerant for the s.e.p. package, while it is 2.5 v tolerant on the ppga package. a logic-low on bsel is defined as 66 mhz. 2.8 test access port (tap) connection due to the voltage levels supported by other components in the test access port (tap) logic, it is recommended that the intel ? celeron? processor be first in the tap chain and followed by any other components within the system. a translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting a 2.5 v input. similar considerations must be made for tck, tms, and trst#. two copies of each signal may be required with each driving a different voltage level. a debug port may be placed at the start and end of the tap chain with the tdi of the first component coming from the debug port and the tdo from the last component going to the debug port. 2.9 maximum ratings table 3 contains the intel ? celeron? processor stress ratings only. functional operation at the absolute maximum and minimum is not implied nor guaranteed. the processor should not receive a clock while subjected to these conditions. functional operating conditions are given in the ac and dc tables. extended exposure to the maximum ratings may affect device reliability. furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid high static voltages or electric fields.
20 datasheet intel ? celeron? processor notes: 1. operating voltage is the voltage to which the component is designed to operate. see table 4 . 2. this rating applies to the v cc core , v cc 5 , and any input (except as noted below) to the processor. 3. parameter applies to cmos, apic, and tap bus signal groups only. 4. the electrical and mechanical integrity of the processor edge fingers are specified to last for 50 insertion/ extraction cycles. 5. s.e.p. package only 6. ppga package only 2.10 processor dc specifications the processor dc specifications in this section are defined for the intel ? celeron? processor. see section 7.0 for signal definitions and section 5.0 for signal listings. most of the signals on the intel celeron processor system bus are in the agtl+ signal group. these signals are specified to be terminated to 1.5 v. the dc specifications for these signals are listed in table 5 . to allow connection with other devices, the clock, cmos, apic, and tap signals are designed to interface at non-agtl+ levels. the dc specifications for these pins are listed in table 6 . table 4 through table 7 list the dc specifications for intel celeron processors operating at 66 mhz intel celeron processor system bus frequencies. specifications are valid only while meeting specifications for case temperature, clock frequency, and input voltages. care should be taken to read all notes associated with each parameter. table 3. intel ? celeron? processor absolute maximum ratings symbol parameter min max unit notes t storage processor storage temperature C40 85 c v cc(all) any processor supply voltage with respect to v ss C0.5 operating voltage + 1.0 v 1, 2 v inagtl+ agtl+ buffer dc input voltage with respect to v ss C0.3 v cc core + 0.7 v v incmos cmos buffer dc input voltage with respect to v ss C0.3 3.3 v 3 i vid max vid pin current 5 ma i slotocc max slotocc# pin current 5 ma 5 i cpupres max cpupres# pin current 5 ma 6 mech max edge fingers 5 mechanical integrity of processor edge fingers 50 insertions/ extractions 4, 5
datasheet 21 intel ? celeron? processor table 4. intel ? celeron? processor voltage and current specifications 1 symbol parameter core freq min typ max unit notes v cc core v cc for processor core 2.00 v 2, 3, 4 v ref agtl+ input reference voltage 2 / 3 v tt C 2% 2 / 3 v tt + 2% v 2%, 11 v cc 1.5 v cc for future v cc cmos 1.365 1.50 1.635 v 1.5 9% v cc 2.5 v cc for v cc cmos 2.375 2.5 2.625 v 2.5 5% v tt agtl+ bus termination voltage 1.365 1.50 1.635 v 1.5 9% 5 baseboard tolerance, static processor core voltage static tolerance level at sc242 pins C0.070 0.100 v 6 baseboard tolerance, transient processor core voltage transient tolerance level at sc242 pins C0.120 0.120 v 6 v cc core tolerance, static processor core voltage static tolerance level at sc242 edge fingers C0.085 0.100 v 7 v cc core tolerance, transient processor core voltage transient tolerance level at sc242 edge fingers C0.140 0.140 v 7 v cc core tolerance, static processor core voltage static tolerance level at ppga processor pins -0.089 0.100 v 8 v cc core tolerance, transient processor core voltage transient tolerance level at ppga processor pins -0.144 0.144 v 8 i cc core i cc for processor core 266 mhz 300 mhz 300a mhz 333 mhz 366 mhz 400 mhz 433 mhz 466 mhz 500 mhz 8.2 9.3 9.3 10.1 11.2 12.2 12.6 13.4 14.2 a 9, 10 i vtt termination voltage supply current 2.7 a 11 i sgnt i cc stop-grant for processor core 266 mhz 300 mhz 300a mhz 333 mhz 366 mhz 400 mhz 433 mhz 466 mhz 500 mhz 1.12 1.15 1.15 1.18 1.21 1.25 1.30 1.35 1.43 a12
22 datasheet intel ? celeron? processor notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. v cc core and i cc core supply the processor core. 3. these voltages are targets only. a variable voltage source should exist on systems in the event that a different voltage is required. 4. use the typical voltage specification with the tolerance specifications to provide correct voltage regulation to the processor. 5. v tt must be held to 1.5 v 9%. it is recommended that v tt be held to 1.5 v 3% while the intel ? celeron? processor system bus is idle. this is measured at the processor edge fingers. 6. these are the tolerance requirements, across a 20 mhz bandwidth, at the sc242 connector pin on the bottom side of the baseboard. the requirements at the sc242 connector pins account for voltage drops (and impedance discontinuities) across the connector, processor edge fingers, and to the processor core. v cc core must return to within the static voltage specification within 100 m s after a transient event. 7. these are the tolerance requirements, across a 20 mhz bandwidth, at the processor edge fingers. the requirements at the processor edge fingers account for voltage drops (and impedance discontinuities) at the processor edge fingers and to the processor core. v cc core must return to within the static voltage specification within 100 m s after a transient event. 8. these are the tolerance requirements, across a 20 mhz bandwidth, at the top of the ppga package. v cc core must return to within the static voltage specification within 100 m s after a transient event. 9. max i cc core measurements are measured at v cc core max voltage (v cc core_typ + maximum static tolerance), under maximum signal loading conditions. 10.voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of v cc core (v cc core_typ ). in this case, the maximum current level for the regulator, i cc core_reg , can be reduced from the specified maximum current i cc core_max and is calculated by the equation: i cc core_reg = i cc core_max v cc core_typ / (v cc core_typ + v cc core tolerance, transient) 11.the current specified is the current required for a single intel celeron processor. a similar amount of current is drawn through the termination resistors on the opposite end of the agtl+ bus, unless single-ended termination is used (see section 2.1 ). 12.the current specified is also for autohalt state. 13.maximum values are specified by design/characterization at nominal v cc core . 14.based on simulation and averaged over the duration of any change in current. use to compute the maximum inductance tolerable and reaction time of the voltage regulator. this parameter is not tested. 15.di cc /dt specifications are measured and specified at the sc242 connector pins. 16.di cc /dt specifications are measured and specified at the ppga packages processor pins. i slp i cc sleep for processor core 266 mhz 300 mhz 300a mhz 333 mhz 366 mhz 400 mhz 433 mhz 466 mhz 500 mhz 0.90 0.94 0.94 0.96 0.97 0.99 1.01 1.03 1.09 a i dslp i cc deep sleep for processor core 0.80 a i cc cmos i cc for v cc cmos 500 ma di cc core /dt power supply current slew rate 20 a/s 13, 14, 15 di cc core /dt power supply current slew rate 240 a/s 13, 14, 16 di cc v tt /dt termination current slew rate 8a/s see table 7 , table 16 , table 17 table 4. intel ? celeron? processor voltage and current specifications 1 symbol parameter core freq min typ max unit notes
datasheet 23 intel ? celeron? processor notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies and cache sizes. 2. v ih and v oh for the intel celeron processor may experience excursions of up to 200 mv above v tt for a single system bus clock. however, input signal drivers must comply with the signal quality specifications in section 3.0 . 3. minimum and maximum v tt are given in table 7 . 4. parameter correlated to measurement into a 25 w resistor terminated to 1.5 v. 5. i oh for the intel celeron processor may experience excursions of up to 12 ma for a single system bus clock. 6. (0 v in 2.0 v +5%). 7. (0 v out 2.0 v +5%). 8. refer to the i/o buffer models for iv characteristics. notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 2. parameter measured at 14 ma (for use with ttl inputs). 3. (0 v in 2.5 v +5%). 4. (0 v out 2.5 v +5%). 2.11 agtl+ system bus specifications it is recommended that the agtl+ bus be routed in a daisy-chain fashion with termination resistors to v tt at each end of the signal trace. these termination resistors are placed electrically between the ends of the signal traces and the v tt voltage supply and generally are chosen to approximate the substrate impedance. the valid high and low levels are determined by the input buffers using a reference voltage called v ref . single ended termination may be possible if trace lengths are tightly controlled, see the intel ? 440ex agpset design guide (order number 290637) or the intel ? celeron? processor (ppga) with the intel ? 440lx agpset design guide (order number 245088) for more information. table 7 below lists the nominal specification for the agtl+ termination voltage (v tt ). the agtl+ reference voltage (v ref ) is generated on the processor substrate (s.e.p. package only) for the processor core, but should be set to 2 / 3 v tt for other agtl+ logic using a voltage divider on table 5. agtl+ signal groups dc specifications 1 symbol parameter min max unit notes v il input low voltage C0.3 0.82 v v ih input high voltage 1.22 v tt v2, 3 r on buffer on resistance 16.67 w 8 i l leakage current for inputs, outputs, and i/o 100 a 6, 7 table 6. non-agtl+ signal group dc specifications 1 symbol parameter min max unit notes v il input low voltage C0.3 0.7 v v ih input high voltage 1.7 2.625 v 2.5 v +5% maximum v ol output low voltage 0.4 v 2 v oh output high voltage n/a 2.625 v all outputs are open- drain to 2.5 v +5% i ol output low current 14 ma i l leakage current for inputs, outputs, and i/o 100 a 3, 4
24 datasheet intel ? celeron? processor the motherboard. it is important that the motherboard impedance be specified and held to a 20% tolerance, and that the intrinsic trace capacitance for the agtl+ signal group traces is known and well-controlled. for more details on agtl+, see the pentium ? ii processor developer's manual (order number 243502) and ap-585, pentium ? ii processor agtl+ guidelines (order number 243330). notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 2. v tt must be held to 1.5 v 9%; di cc vtt /dt is specified in table 4 . it is recommended that v tt be held to 1.5 v 3% while the intel celeron processor system bus is idle. this is measured at the processor edge fingers. 3. v ref is generated on the processor substrate to be 2 / 3 v tt nominally with the s.e.p. package. it must be created on the motherboard for processors in the ppga package. 2.12 intel ? celeron? processor system bus ac specifications the intel ? celeron? processor system bus timings specified in this section are defined at the intel celeron processor edge fingers and the processor core pads. timings specified at the processor edge fingers only apply to the s.e.p. package and timings given at the processor core pads apply to both the s.e.p. package and the ppga package. unless otherwise specified, timings are tested at the processor core during manufacturing. timings at the processor edge fingers are specified by design characterization. see section 7.0 for the intel celeron processor signal definitions. note that at 66 mhz system bus operation, the intel celeron processor timings at the processor edge fingers are identical to the pentium ii processor timings at the edge fingers. see the pentium ? ii processor at 233, 266, 300, and 333 mhz (order number 243335) for more detail. table 8 through table 20 list the ac specifications associated with the intel celeron processor system bus. these specifications are broken into the following categories: table 8 through table 10 contain the system bus clock specifications, table 11 and table 12 contain the agtl+ specifications, table 14 and table 15 are the cmos signal group specifications, table 16 contains timings for the reset conditions, table 17 and table 18 cover apic bus timing, and table 19 and table 20 cover tap timing. for each pair of tables, the first table contains timing specifications for measurement or simulation at the processor edge fingers. the second table contains specifications for simulation at the processor core pads. all intel celeron processor system bus ac specifications for the agtl+ signal group are relative to the rising edge of the bclk input. all agtl+ timings are referenced to v ref for both 0 and 1 logic levels unless otherwise specified. the timings specified in this section should be used in conjunction with the i/o buffer models provided by intel. these i/o buffer models, which include package information, are available for the pentium ii processor in quad format as the pentium ? ii processor i/o buffer models , quad xtk format (electronic form). agtl+ layout guidelines are also available in ap-585, pentium ? ii processor agtl+ guidelines (order number 243330). care should be taken to read all notes associated with a particular timing parameter. table 7. intel ? celeron? processor agtl+ bus specifications 1 symbol parameter min typ max units notes v tt bus termination voltage 1.365 1.50 1.635 v 1.5 v 9% 2 r tt termination resistor 56 w 5% v ref bus reference voltage 2 / 3 v tt v 2% 3
datasheet 25 intel ? celeron? processor notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 2. all ac timings for the agtl+ signals are referenced to the bclk rising edge at 0.70 v at the processor edge fingers. this reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to receive the signal with a reference at 1.25 v. all agtl+ signal timings (address bus, data bus, etc.) are referenced at 1.00 v at the processor edge fingers. 3. all ac timings for the cmos signals are referenced to the bclk rising edge at 0.70 v at the processor edge fingers. this reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to receive the signal with a reference at 1.25 v. all cmos signal timings (compatibility signals, etc.) are referenced at 1.25 v at the processor edge fingers. 4. the internal core clock frequency is derived from the intel celeron processor system bus clock. the system bus clock to core clock ratio is determined during initialization. table 10 shows the supported ratios for each processor. 5. the bclk period allows a +0.5 ns tolerance for clock driver variation. 6. this specification applies to intel celeron processors when operating at a system bus frequency of 66 mhz. 7. the bclk offset time is the absolute difference needed between the bclk signal arriving at the intel celeron processor edge finger at 0.5 v vs. arriving at the core logic at 1.25 v. the positive offset is needed to account for the delay between the sc242 connector and processor core. the positive offset ensures both the processor core and the core logic receive the bclk edge concurrently. 8. see section 3.1 for intel celeron processor system bus clock signal quality specifications. 9. not 100% tested. specified by design characterization as a clock driver requirement. table 8. intel ? celeron? processor system bus ac specifications (clock) at the processor edge fingers for the s.e.p. package 1, 2, 3 t# parameter min nom max unit figure notes system bus frequency 66.67 mhz t1: bclk period 15.0 ns 6 4, 5, 6 t1b: sc242 to core logic bclk offset 0.78 ns 6 absolute value 7,8 t2: bclk period stability 300ps see table 9 t3: bclk high time 4.44 ns 6 @>2.0 v 6 t4: bclk low time 4.44 ns 6 @<0.5 v 6 t5: bclk rise time 0.84 2.31 ns 6 (0.5 vC2.0 v) 6, 9 t6: bclk fall time 0.84 2.31 ns 6 (2.0 vC0.5 v) 6, 9
26 datasheet intel ? celeron? processor notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 2. all ac timings for the agtl+ signals are referenced to the bclk rising edge at 1.25 v at the processor core pin. all agtl+ signal timings (address bus, data bus, etc.) are referenced at 1.00 v at the processor core pins. 3. all ac timings for the cmos signals are referenced to the bclk rising edge at 1.25 v at the processor core pin. all cmos signal timings (compatibility signals, etc.) are referenced at 1.25 v at the processor core pins. 4. the internal core clock frequency is derived from the intel celeron processor system bus clock. the system bus clock to core clock ratio is determined during initialization. table 10 shows the supported ratios for each processor. 5. the bclk period allows a +0.5 ns tolerance for clock driver variation. 6. this specification applies to the intel celeron processor when operating at a system bus frequency of 66 mhz. 7. see section 3.1 for intel celeron processor system bus clock signal quality specifications. 8. due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be used that is designed to meet the period stability specification into a test load of 10 to 20 pf. this should be measured on the rising edges of adjacent bclks crossing 1.25 v at the processor core pin . the jitter present must be accounted for as a component of bclk timing skew between devices. 9. the clock drivers closed loop jitter bandwidth must be set low to allow any pll-based device to track the jitter created by the clock driver. the C20 db attenuation point, as measured into a 10 to 20 pf load, should be less than 500 khz. this specification may be ensured by design characterization and/or measured with a spectrum analyzer. 10.not 100% tested. specified by design characterization as a clock driver requirement. notes: 1. contact your local intel representative for the latest information on processor frequencies and/or frequency multipliers. 2. while other bus ratios are defined, operation at frequencies other than those listed are not supported. table 9. intel ? celeron? processor system bus ac specifications (clock) at the processor core pins for both s.e.p. and ppga packages 1, 2, 3 t# parameter min nom max unit figure notes system bus frequency 66.67 mhz t1: bclk period 15.0 ns 6 4, 5, 6 t2: bclk period stability 300 ps 6 6, 8, 9 t3: bclk high time 4.94 ns 6 @>2.0 v 6 t4: bclk low time 4.94 ns 6 @<0.5 v 6 t5: bclk rise time 0.34 1.36 ns 6 (0.5 vC2.0 v) 6, 10 t6: bclk fall time 0.34 1.36 ns 6 (2.0 vC0.5 v) 6, 10 table 10. valid intel ? celeron? processor system bus, core frequency 1, 2 core frequency (mhz) bclk frequency (mhz) frequency multiplier 266 66 4 300 66 4.5 333 66 5 366 66 5.5 400 66 6 433 66 6.5 466 66 7 500 66 7.5
datasheet 27 intel ? celeron? processor notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 2. not 100% tested. specified by design characterization. 3. all ac timings for the agtl+ signals are referenced to the bclk rising edge at 0.50 v at the processor edge fingers. all agtl+ signal timings (compatibility signals, etc.) are referenced at 1.00 v at the processor edge fingers. 4. this specification applies to intel celeron processors operating with a 66 mhz intel celeron processor system bus only. 5. valid delay timings for these signals are specified into 50 w to 1.5 v and with v ref at 1.0 v. 6. a minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of trdy#. 7. reset# can be asserted (active) asynchronously, but must be deasserted synchronously. 8. specification is for a minimum 0.40 v swing. 9. specification is for a maximum 1.0 v swing. 10.after v cc core , and bclk become stable. notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 2. these specifications are tested during manufacturing. 3. all ac timings for the agtl+ signals are referenced to the bclk rising edge at 1.25 v at the processor core pin. all agtl+ signal timings (compatibility signals, etc.) are referenced at 1.00 v at the processor core pins. 4. this specification applies to the intel celeron processor operating with a 66 mhz intel celeron processor system bus only. 5. valid delay timings for these signals are specified into 25 w to 1.5 v and with v ref at 1.0 v. 6. a minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of trdy#. 7. reset# can be asserted (active) asynchronously, but must be deasserted synchronously. 8. specification is for a minimum 0.40 v swing. 9. specification is for a maximum 1.0 v swing. 10.after v cc core and bclk become stable. table 11. intel ? celeron? processor system bus ac specifications (agtl+ signal group) at the processor edge fingers for the s.e.p. package 1, 2, 3, 4 t# parameter min max unit figure notes t7: agtl+ output valid delay 1.07 6.37 ns 7 4, 5 t8: agtl+ input setup time 1.96 ns 8 4, 6, 7, 8 t9: agtl+ input hold time 1.53 ns 8 4, 9 t10: reset# pulse width 1.00 ms 10 10 table 12. intel ? celeron? processor system bus ac specifications (agtl+ signal group) at the processor core pins for the s.e.p. package 1, 2, 3, 4 t# parameter min max unit figure notes t7: agtl+ output valid delay 0.17 5.16 ns 7 5 t8: agtl+ input setup time 2.10 ns 8 5, 6, 7, 8 t9: agtl+ input hold time 0.77 ns 8 9 t10: reset# pulse width 1.00 ms 10 7, 10
28 datasheet intel ? celeron? processor notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. these specifications are tested during manufacturing. 3. all ac timings for the agtl+ signals are referenced to the bclk rising edge at 1.25 v at the processor pin. all gtl+ signal timings (compatibility signals, etc.) are referenced at 1.00 v at the processor pins. 4. this specification applies to the processor operating with a 66 mhz system bus only. 5. valid delay timings for these signals are specified into 25 w to 1.5 v and with v ref at 1.0 v. 6. a minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of trdy#. 7. reset# can be asserted (active) asynchronously, but must be deasserted synchronously. 8. after v cc core and bclk become stable. notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 2. not 100% tested. specified by design characterization. 3. all ac timings for the cmos signals are referenced to the bclk rising edge at 0.50 v at the processor edge fingers. all cmos signal timings (address bus, data bus, etc.) are referenced at 1.25 v. 4. these signals may be driven asynchronously. 5. this specification only applies when the apic is enabled and the lint1 or lint0 pin is configured as an edge-triggered interrupt with fixed delivery; otherwise, specification t14 applies. pwrgood must remain below v il,max ( table 5 ) until all the voltage planes meet the voltage tolerance specifications in table 4 and bclk has met the bclk ac specifications in table 9 for at least 10 clock cycles. pwrgood must rise glitch-free and monotonically to 2.5 v. 6. when driven inactive or after v cc core , and bclk become stable. 7. if the bclk signal meets its ac specification within 150 ns of turning on, then the pwrgood inactive pulse width specification (t15) is waived and bclk may start after pwrgood is asserted. pwrgood must still remain below v il,max until all the voltage planes meet the voltage tolerance specifications. table 13. processor system bus ac specifications (agtl+ signal group) at the processor core pins for the ppga package 1, 2, 3, 4 t# parameter min max unit figure notes t7: agtl+ output valid delay 0.30 4.43 ns 5 t8: agtl+ input setup time 2.10 ns 5, 6, 7 t9: agtl+ input hold time 0.85 ns t10: reset# pulse width 1.00 ms 7, 8 table 14. intel ? celeron? processor system bus ac specifications (cmos signal group) at the processor edge fingers for s.e.p. package 1, 2, 3, 4 t# parameter min max unit figure notes t14: cmos input pulse width, except pwrgood 2 bclks 7 active and inactive states t14b: lint[1:0] input pulse width 6 bclks 7 5 t15: pwrgood inactive pulse width 10 bclks 7, 10 6, 7
datasheet 29 intel ? celeron? processor notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 2. these specifications are tested during manufacturing. 3. all ac timings for the cmos signals are referenced to the bclk rising edge at 1.25 v at the processor core pins. all cmos signal timings (address bus, data bus, etc.) are referenced at 1.25 v. 4. these signals may be driven asynchronously. 5. this specification only applies when the apic is enabled and the lint1 or lint0 pin is configured as an edge-triggered interrupt with fixed delivery; otherwise, specification t14 applies. 6. when driven inactive or after v cc core , and bclk become stable. 7. if the bclk signal meets its ac specification within 150 ns of turning on, then the pwrgood inactive pulse width specification (t15) is waived and bclk may start after pwrgood is asserted. pwrgood must still remain below v il,max until all the voltage planes meet the voltage tolerance specifications. pwrgood must remain below v il,max ( table 5 ) until all the voltage planes meet the voltage tolerance specifications in table 4 and bclk has met the bclk ac specifications in table 9 for at least 10 clock cycles. pwrgood must rise glitch-free and monotonically to 2.5 v. notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. table 15. intel ? celeron? processor system bus ac specifications (cmos signal group) at the processor core pins for both s.e.p. and ppga packages 1, 2, 3, 4 t# parameter min max unit figure notes t14: cmos input pulse width, except pwrgood 2 bclks 7 active and inactive states t14b: lint[1:0] input pulse width (s.e.p.p. only) 6 bclks 7 5 t15: pwrgood inactive pulse width 10 bclks 7,10 6, 7 table 16. intel ? celeron? processor system bus ac specifications (reset conditions) 1 t# parameter min max unit figure notes t16: reset configuration signals (a[14:5]#, br0#, flush#, init#) setup time 4 bclks 9 before deassertion of reset# t17: reset configuration signals (a[14:5]#, br0#, flush#, init#) hold time 2 20 bclks 9 after clock that deasserts reset#
30 datasheet intel ? celeron? processor notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 2. not 100% tested. specified by design characterization. 3. all ac timings for the apic i/o signals are referenced to the picclk rising edge at 0.7 v at the processor edge fingers. all apic i/o signal timings are referenced at 1.25 v at the processor edge fingers. 4. this specification applies to intel celeron processors operating with a 66 mhz intel celeron processor system bus only. 5. referenced to picclk rising edge. 6. for open drain signals, valid delay is synonymous with float delay. 7. valid delay timings for these signals are specified to 2.5 v +5%. notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 2. these specifications are tested during manufacturing. 3. all ac timings for the apic i/o signals are referenced to the picclk rising edge at 1.25 v at the processor core pins. all apic i/o signal timings are referenced at 1.25 v at the processor core pins. 4. this specification applies to intel celeron processors operating with a 66 mhz intel celeron processor system bus only. 5. referenced to picclk rising edge. 6. for open drain signals, valid delay is synonymous with float delay. 7. valid delay timings for these signals are specified to 2.5 v +5%. table 17. intel ? celeron? processor system bus ac specifications (apic clock and apic i/o) at the processor edge fingers for s.e.p. package 1, 2, 3, 4 t# parameter min max unit figure notes t21: picclk frequency 2.0 33.3 mhz t22: picclk period 30.0 500.0 ns 6 t23: picclk high time 12.0 ns 6 t24: picclk low time 12.0 ns 6 t25: picclk rise time 0.25 3.0 ns 6 t26: picclk fall time 0.25 3.0 ns 6 t27: picd[1:0] setup time 8.5 ns 8 5 t28: picd[1:0] hold time 3.0 ns 8 5 t29: picd[1:0] valid delay 3.0 12.0 ns 7 5, 6, 7 table 18. intel ? celeron? processor system bus ac specifications (apic clock and apic i/o) at the processor core pins for s.e.p. and ppga packages 1, 2, 3, 4 t# parameter min max unit figure notes t21: picclk frequency 2.0 33.3 mhz t22: picclk period 30.0 500.0 ns 6 t23: picclk high time 11.0 ns 6 @>2.0v t24: picclk low time 11.0 ns 6 @<0.5v t25: picclk rise time 0.25 3.0 ns 6 (0.5v-2.0v) t26: picclk fall time 0.25 3.0 ns 6 (2.0v-0.5v) t27: picd[1:0] setup time 8.0 ns 8 5 t28: picd[1:0] hold time 2.5 ns 8 5 t29: picd[1:0] valid delay 1.5 10.0 ns 7 5, 6, 7
datasheet 31 intel ? celeron? processor notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 2. all ac timings for the tap signals are referenced to the tck rising edge at 0.70 v at the processor edge fingers. all tap signal timings (tms, tdi, etc.) are referenced at 1.25 v at the processor edge fingers. 3. not 100% tested. specified by design characterization. 4. 1 ns can be added to the maximum tck rise and fall times for every 1 mhz below 16.667 mhz. 5. referenced to tck rising edge. 6. referenced to tck falling edge. 7. valid delay timing for this signal is specified to 2.5 v +5%. 8. non-test outputs and inputs are the normal output or input signals (besides tck, trst#, tdi, tdo, and tms). these timings correspond to the response of these signals due to tap operations. 9. during debug port operation, use the normal specified timings rather than the tap signal timings. table 19. intel ? celeron? processor system bus ac specifications (tap connection) at the processor edge fingers for s.e.p. package 1, 2, 3 t# parameter min max unit figure notes t30: tck frequency 16.667 mhz t31: tck period 60.0 ns 6 t32: tck high time 25.0 ns 6 @1.7 v t33: tck low time 25.0 ns 6 @0.7 v t34: tck rise time 5.0 ns 6 (0.7 vC1.7 v) 4 t35: tck fall time 5.0 ns 6 (1.7 vC0.7 v) 4 t36: trst# pulse width 40.0 ns 12 asynchronous t37: tdi, tms setup time 5.5 ns 11 5 t38: tdi, tms hold time 14.5 ns 11 5 t39: tdo valid delay 2.0 13.5 ns 11 6, 7 t40: tdo float delay 28.5 ns 11 6, 7 t41: all non-test outputs valid delay 2.0 27.5 ns 11 6, 8, 9 t42: all non-test inputs setup time 27.5 ns 11 6, 8, 9 t43: all non-test inputs setup time 5.5 ns 11 5, 8, 9 t44: all non-test inputs hold time 14.5 ns 11 5, 8, 9
32 datasheet intel ? celeron? processor notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 2. all ac timings for the tap signals are referenced to the tck rising edge at 1.25 v at the processor core pins. all tap signal timings (tms, tdi, etc.) are referenced at 1.25 v at the processor core pins. 3. these specifications are tested during manufacturing, unless otherwise noted. 4. 1 ns can be added to the maximum tck rise and fall times for every 1 mhz below 16.667 mhz. 5. referenced to tck rising edge. 6. referenced to tck falling edge. 7. valid delay timing for this signal is specified to 2.5 v +5%. 8. non-test outputs and inputs are the normal output or input signals (besides tck, trst#, tdi, tdo, and tms). these timings correspond to the response of these signals due to tap operations. 9. during debug port operation, use the normal specified timings rather than the tap signal timings. 10.not 100% tested. specified by design characterization. table 20. intel ? celeron? processor system bus ac specifications (tap connection) at the processor core pins for both s.e.p. and ppga packages 1, 2, 3 t# parameter min max unit figure notes t30: tck frequency 16.667 mhz t31: tck period 60.0 ns 6 t32: tck high time 25.0 ns 6 @1.7 v 10 t33: tck low time 25.0 ns 6 @0.7 v 10 t34: tck rise time 5.0 ns 6 (0.7 vC1.7 v) 4, 10 t35: tck fall time 5.0 ns 6 (1.7 vC0.7 v) 4, 10 t36: trst# pulse width 40.0 ns 12 asynchronous 10 t37: tdi, tms setup time 5.0 ns 11 5 t38: tdi, tms hold time 14.0 ns 11 5 t39: tdo valid delay 1.0 10.0 ns 11 6, 7 t40: tdo float delay 25.0 ns 11 6, 7, 10 t41: all non-test outputs valid delay 2.0 25.0 ns 11 6, 8, 9 t42: all non-test inputs setup time 25.0 ns 11 6, 8, 9, 10 t43: all non-test inputs setup time 5.0 ns 11 5, 8, 9 t44: all non-test inputs hold time 13.0 ns 11 5, 8, 9
datasheet 33 intel ? celeron? processor note: for figure 3 through figure 9 , the following apply: 1. figure 3 through figure 9 are to be used in conjunction with table 8 through table 20 . 2. all ac timings for the agtl+ signals at the processor edge fingers are referenced to the bclk rising edge at 0.50 v. this reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to receive the signal with a reference at 1.25 v. all agtl+ signal timings (address bus, data bus, etc.) are referenced at 1.00 v at the processor edge fingers. 3. all ac timings for the agtl+ signals at the processor core pins are referenced to the bclk rising edge at 1.25 v. all agtl+ signal timings (address bus, data bus, etc.) are referenced at 1.00 v at the processor core pins. 4. all ac timings for the cmos signals at the processor edge fingers are referenced to the bclk rising edge at 0.50 v. this reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to receive the signal with a reference at 1.25 v. all cmos signal timings (compatibility signals, etc.) are referenced at 1.25 v at the processor edge fingers. 5. all ac timings for the apic i/o signals at the processor edge fingers are referenced to the picclk rising edge at 0.7 v. all apic i/o signal timings are referenced at 1.25 v at the processor edge fingers. 6. all ac timings for the tap signals at the processor edge fingers are referenced to the tck rising edge at 0.70 v. all tap signal timings (tms, tdi, etc.) are referenced at 1.25 v at the processor edge fingers. figure 2. bclk to core logic offset figure 3. bclk*, picclk, and tck generic clock waveform bclk at edge fingers 0.5v bclk at core logic 1.25v t1b' 1.7v (2.0v*) 1.25v 0.7v (0.5v*) t r t p t f t h t l clk t r = t5, pt25, t34 (rise time) t f = t6, t26, t35 (fall time) t h = t3, t23, t32 (high time) t l = t4, t24, t33 (low time) t p = t1, t22, t31 (blck, tck, picclk period) note: bclk is referenced to 0.5 v and 2.0 v. picclk and tck are referenced to 0.7 v and 1.7 v
34 datasheet intel ? celeron? processor figure 4. intel ? celeron? processor system bus valid delay timings figure 5. intel ? celeron? processor system bus setup and hold timings figure 6. intel ? celeron? processor system bus reset and configuration timings clk signal t x t x t pw v valid valid t x t7, t11, t29 (valid delay) = t pw t14, t15 (pulse wdith) = v 1.0v for gtl+ signal group; 1.25v for cmos, apic and jtag signal groups = clk signal v valid t s t8, t12, t27 (setup time) = t h t9, t13, t28 (hold time) = v 1.0v for gtl+ signal group; 1.25v for cmos, apic and jtag signal groups = t h t s valid t v t w t x t u t t bclk reset# configuration (a[14:5]#, br0#, flush#, int#) t t = t9 (gtl+ input hold time) t u = t8 (gtl+ input setup time) t v = t10 (reset# pulse width) t w = t16 (reset configuration signals (a[14:5]#, br0#, flush#, init#) setup t x = t17 (reset configuration signals (a[14:5]#, br0#, flush#, init#) hold
datasheet 35 intel ? celeron? processor figure 7. power-on reset and configuration timings figure 8. test timings (tap connection) figure 9. test reset timings t a bclk vcc core v ref t a = t15 (pwrgood inactive pulse width) t b = t10 (reset# pulse width) t b pwrgood reset# tck t di, tms input signals tdo output signals 1.25v t v t w t r t s t x t u t y t z 1.25v t r t43 (all non-test inputs setup time) = t s t44 (all non-test inputs hold time) = t u t40 (tdo float delay) = t v t37 (tdi, tms setup time) = t w t38 (tdi, tms hold time) = t x t39 (tdo valid delay) = t y t41 (all non-test outputs valid delay) = t z t42 (all non-test outputs float delay) = trst# pcb 773 1.25v t q t q t37 (trst# pulse width) =
36 datasheet intel ? celeron? processor 3.0 system bus signal simulations signals driven on the intel ? celeron? processor system bus should meet signal quality specifications to ensure that the components read data properly and to ensure that incoming signals do not affect the long term reliability of the component. specifications are provided for simulation at the processor core; guidelines are provided for correlation to the processor edge fingers. these edge finger guidelines are intended for use during testing and measurement of system signal integrity. violations of these guidelines are permitted, but if they occur, simulation of signal quality at the processor core should be performed to ensure that no violations of signal quality specifications occur. meeting the specifications at the processor core in table 21 , table 23 , and table 25 ensures that signal quality effects will not adversely affect processor operation, but does not necessarily guarantee that the guidelines in table 22 , table 24 , and table 26 will be met. 3.1 intel ? celeron? processor system bus clock (bclk) signal quality specifications and measurement guidelines table 21 describes the signal quality specifications at the processor core for the intel ? celeron? processor system bus clock (bclk) signal. table 22 describes guidelines for signal quality measurement at the processor edge fingers. figure 10 describes the signal quality waveform for the system bus clock at the processor core pins; figure 11 describes the signal quality waveform for the system bus clock at the processor edge fingers. notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 2. this is the intel celeron processor system bus clock overshoot and undershoot specification for 66 mhz system bus operation. 3. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the bclk signal can dip back to after passing the v ih (rising) or v il (falling) voltage limits. this specification is an absolute value. table 21. bclk signal quality specifications for simulation at the processor core for both s.e.p. and ppga packages 1 t# parameter min nom max unit figure notes v1: bclk v il 0.5 v 14 v2: bclk v ih 2.0 v 14 2 v3: v in absolute voltage range C0.7 3.5 v 14 2 v4: rising edge ringback 1.7 v 14 3 v5: falling edge ringback 0.7 v 14 3
datasheet 37 intel ? celeron? processor notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 2. this is the intel celeron processor system bus clock overshoot and undershoot measurement guideline. 3. the rising and falling edge ringback voltage guideline is the minimum (rising) or maximum (falling) absolute voltage the bclk signal may dip back to after passing the v ih (rising) or v il (falling) voltage limits. this guideline is an absolute value. 4. the bclk at the processor edge fingers may have a dip or ledge midway on the rising or falling edge. the midpoint voltage level of this ledge should be within the range of the guideline. 5. the ledge (v7) is allowed to have peak-to-peak oscillation as given in the guideline. figure 10. bclk, tck, picclk generic clock waveform at the processor core pins table 22. bclk signal quality guidelines for edge finger measurement on the s.e.p. package 1 t# parameter min nom max unit figure notes v1: bclk v il 0.5 v 14 v2: bclk v ih 2.0 v 14 v3: v in absolute voltage range C0.5 3.3 v 14 2 v4: rising edge ringback 2.0 v 14 3 v5: falling edge ringback 0.5 v 14 3 v6: t line ledge voltage 1.0 1.7 v 14 at ledge midpoint 4 v7: t line ledge oscillation 0.2 v 14 peak-to-peak 5 v2 v1 v3 v3 t3 v5 v4 t6 t4 t5
38 datasheet intel ? celeron? processor 3.2 agtl+ signal quality specifications and measurement guidelines many scenarios have been simulated to generate a set of agtl+ layout guidelines which are available in ap-585, pentium ? ii processor agtl+ guidelines (order number 243330). refer to the pentium ? ii processor developer's manual (order number 243502) for the agtl+ buffer specification. table 23 provides the agtl+ signal quality specifications for intel ? celeron? processors for use in simulating signal quality at the processor core. table 24 provides agtl+ signal quality guidelines for measuring and testing signal quality at the processor edge fingers. figure 12 describes the signal quality waveform for agtl+ signals at the processor core and edge fingers. for more information on the agtl+ interface, see the pentium ? ii processor developer's manual (order number 243502). notes: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 2. specifications are for the edge rate of 0.3 - 0.8 v/ns. see figure 12 for the generic waveform. 3. all values specified by design characterization. 4. this specification applies to intel celeron processors operating with a 66 mhz intel celeron processor system bus only. 5. ringback below v ref + 20 mv is not supported. figure 11. bclk, tck, picclk generic clock waveform at the processor edge fingers t3 v3 v5 v3 v 2 v 1 v7 v6 t6 t4 t5 v4 table 23. agtl+ signal groups ringback tolerance specifications at the processor core for both the s.e.p. and ppga packages 1, 2, 3 t# parameter min unit figure notes a : overshoot 100 mv 15 4 t : minimum time at high 1.00 ns 15 4 r : amplitude of ringback C100 mv 15 4, 5 f : final settling voltage 100 mv 15 4 d : duration of squarewave ringback n/a ns 15
datasheet 39 intel ? celeron? processor notes: 1. unless otherwise noted, all guidelines in this table apply to all intel ? celeron? processor frequencies. 2. guidelines are for the edge rate of 0.3 - 0.8 v/ns. see figure 12 for the generic waveform. 3. all values specified by design characterization. 4. this guideline applies to intel celeron processors operating with a 66 mhz system bus only. 5. ringback below v ref + 250 mv is not supported. table 24. agtl+ signal groups ringback tolerance guidelines for edge finger measurement on the s.e.p. package 1, 2, 3 t# parameter min unit figure notes a : overshoot 100 mv 15 t : minimum time at high 1.5 ns 15 4 r : amplitude of ringback C250 mv 15 4, 5 f : final settling voltage 250 mv 15 4 d : duration of squarewave ringback n/a ns 15 figure 12. low to high agtl+ receiver ringback tolerance t a r f v start v +0.2 ref v ref v C0.2 ref time clock note: high to low case is analogous. d 0.7v clk ref
40 datasheet intel ? celeron? processor 3.3 non-agtl+ signal quality specifications and measurement guidelines there are three signal quality parameters defined for non-agtl+ signals: overshoot/undershoot, ringback, and settling limit. all three signal quality parameters are shown in figure 13 for the non- agtl+ signal group. 3.3.1 overshoot/undershoot guidelines overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage or below v ss . the overshoot/undershoot guideline limits transitions beyond v cc or v ss due to the fast signal edge rates. (see figure 13 for non-agtl+ signals.) the processor can be damaged by repeated overshoot events on 2.5 v tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). however, excessive ringback is the dominant detrimental system timing effect resulting from overshoot/undershoot (i.e., violating the overshoot/undershoot guideline will make satisfying the ringback specification difficult). the overshoot/undershoot guideline is 0.7 v and assumes the absence of diodes on the input. these guidelines should be verified in simulations without the on-chip esd protection diodes present because the diodes will begin clamping the 2.5 v tolerant signals beginning at approximately 0.7 v above the 2.5 v supply and 0.7 v below v ss . if signals are not reaching the clamping voltage, this will not be an issue. a system should not rely on the diodes for overshoot/undershoot protection as this will negatively affect the life of the components and make meeting the ringback specification very difficult. figure 13. non-agtl+ overshoot/undershoot, settling limit, and ringback undershoot overshoot settling limit settling limit rising-edge ringback falling-edge ringback v lo v ss time 000767b v = hi v cc 2.5
datasheet 41 intel ? celeron? processor 3.3.2 ringback specification ringback refers to the amount of reflection seen after a signal has switched. the ringback specification is the voltage that the signal rings back to after achieving its maximum absolute value . (see figure 13 for an illustration of ringback.) excessive ringback can cause false signal detection or extend the propagation delay. the ringback specification applies to the input pin of each receiving agent. violations of the signal ringback specification are not allowed under any circumstances for non-agtl+ signals. ringback can be simulated with or without the input protection diodes that can be added to the input buffer model. however, signals that reach the clamping voltage should be evaluated further. see table 25 for the signal ringback specifications for non-agtl+ signals for simulations at the processor core, and table 26 for guidelines on measuring ringback at the edge fingers. note: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. note: 1. unless otherwise noted, all specifications in this table apply to all intel ? celeron? processor frequencies. 3.3.3 settling limit guideline settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition. the amount allowed is 10 percent of the total signal swing (v hi C v lo ) above and below its final value. a signal should be within the settling limits of its final value, when either in its high state or low state, before it transitions again. signals that are not within their settling limit before transitioning are at risk of unwanted oscillations which could jeopardize signal integrity. simulations to verify settling limit may be done either with or without the input protection diodes present. violation of the settling limit guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of the ringing increasing in the subsequent transitions. table 25. signal ringback specifications for non-agtl+ signal simulation at the processor core for both s.e.p. and ppga packages 1 input signal group transition maximum ringback (with input diodes present) unit figure notes non-agtl+ signals 0 ? 11.7v16 non-agtl+ signals 1 ? 00.7v16 table 26. signal ringback guidelines for non-agtl+ signal edge finger measurement on the s.e.p. package 1 input signal group transition maximum ringback (with input diodes present) unit figure notes non-agtl+ signals 0 ? 12.0v16 non-agtl+ signals 1 ? 00.7v16
42 datasheet intel ? celeron? processor 4.0 thermal specifications and design considerations 4.1 thermal specifications table 27 and table 28 provide both the processor power and heat sink design target for intel ? celeron? processors. processor power is defined as the total power dissipated by the processor core and its package. therefore, the s.e.p. packages processor power would also include power dissipated by the agtl+ termination resistors. the overall system chassis thermal design must comprehend the entire processor power. the heat sink design target consists of only the processor core, which dissipates the majority of the thermal power. systems should design for the highest possible thermal power, even if a processor with a lower thermal dissipation is planned. the processors heatslug is the attach location for all thermal solutions. the maximum and minimum case temperatures are also specified in table 27 and table 28 . a thermal solution should be designed to ensure the temperature of the case never exceeds these specifications. notes: 1. these values are specified at nominal v cc core for the processor core. 2. processor power is power generated from the s.e.p. packages substrate, which includes the processor core and the agtl+ termination resistors. 3. heat sink design target refers to the power consumption of the processor core. notes: 1. these values are specified at nominal v cc core for the processor core. 2. processor power and heat sink design target are the same value because the ppga package does not have agtl+ termination resistors. table 27. intel ? celeron? processor power for the s.e.p. package 1 processor core frequency (mhz) l2 cache size (kb) processor power (w) 2 heat sink design target (w) 3 minimum t case (c) maximum t case (c) 266 0 16.6 16.0 5 85 300 0 18.4 17.8 5 85 300a 128 18.4 17.8 5 85 333 128 20.2 19.7 5 85 366 128 22.2 21.7 5 85 400 128 24.2 23.7 5 85 433 128 24.6 24.1 5 85 table 28. intel ? celeron? processor power for the ppga package 1,2 processor core frequency (mhz) l2 cache size (kb) processor power (w) heat sink design target (w) minimum t case (c) maximum t case (c) 300a 128 17.8 17.8 5 85 333 128 19.7 19.7 5 85 366 128 21.7 21.7 5 85 400 128 23.7 23.7 5 85 433 128 24.1 24.1 5 85 466 128 25.6 25.6 5 70 500 128 27.0 27.0 5 70
datasheet 43 intel ? celeron? processor 4.1.1 thermal diode the intel ? celeron? processor incorporates an on-die diode that can be used to monitor the die temperature. a thermal sensor located on the motherboard may monitor the die temperature of the intel celeron processor for thermal management purposes. table 29 and table 30 provide the diode parameter and interface specifications. notes: 1. intel does not support or recommend operation of the thermal diode under reverse bias. 2. at room temperature with a forward bias of 630 mv. 3. n_ideality is the diode ideality factor parameter, as represented by the diode equation: i-io(e (vd*q)/(nkt) - 1). 4. not 100% tested. specified by design characterization. 4.2 thermal parameters this section defines the terms used for intel ? celeron? processor thermal analysis. 4.2.1 ambient temperature ambient temperature, t a , is the temperature of the ambient air surrounding the package. the design recommendation of t a is 45 c. in a system environment, ambient temperature is the temperature of the air upstream from the package and in its close vicinity; or in an active cooling system, it is the inlet air to the active cooling device. 4.2.2 thermal resistance the thermal resistance value for the case to ambient, q ca is used as a measure of the cooling solutions performance. q ca is comprised of the case to sink thermal, q cs and the sink to ambient thermal resistance, q sa . q cs is a measure of the thermal resistance along the heat flow path from the top of the heatslug to the bottom of the cooling solution. this value is strongly dependent on the material, conductivity, and thickness of the thermal interface used. q sa is a measure of the thermal resistance from the top of the cooling solution to the local ambient air. q sa values depend on the material, thermal conductivity, and geometry of the thermal cooling solution as well as on the airflow rates. table 29. thermal diode parameters 4 symbol min typ max unit notes i forward bias 5 500 ua 1 n_ideality 1.0000 1.0065 1.0173 2,3 table 30. thermal diode interface pin name sc242 connector signal # 370-pin socket pin # pin description thermdp b14 al31 diode anode (p junction) thermdn b15 al29 diode cathode (n junction)
44 datasheet intel ? celeron? processor 4.2.3 thermal solution performance all processor thermal solutions should attach to the processors heatslug. the thermal solution must adequately control the processors case temperatures below the maximum and above the minimum specified in table 27 . the performance of any thermal solution is defined as the thermal resistance between the case temperature and the ambient air around the processor ( q ca ). the lower the thermal resistance between the case and the ambient air, the more efficient the thermal solution is. the required q ca is dependent upon the maximum allowed case temperature (t case ), the local ambient temperature (t la ) and the maximum power dissipation of the processor. q ca = (t case C t la ) / p d the case temperature and device power is listed in table 27 . t la is a function of the system design. table 31 provides an example of the resulting thermal solution performance required for a 266 mhz intel celeron processor at different ambient air temperatures around the processor. a critical but controllable factor to decrease the value of q cs is management of the thermal interface between the case and heat sink. the other controllable factor ( q sa ) is determined by the design of the heat sink and airflow around the heat sink. 4.3 thermal solution attach methods it is recommended that the intel celeron processor be integrated with an intel designed heat sink and clip. these components are available from major manufacturers. table 31. example thermal solution performance for 266 mhz intel ? celeron? processor at power of 16.6 watts local ambient temperature (t la ) 35 c 40 c 45 c q ca (c/watt) 3.01 2.71 2.41
datasheet 45 intel ? celeron? processor 5.0 mechanical specifications there are two package technologies which intel ? celeron? processors use. they are the s.e.p. package and the ppga package. the s.e.p. package contains the processor core and passive components, while the ppga package does not have passive components. the processor edge connector defined in this document is referred to as the sc242 connector. see the sc242 design guidelines (order number 243397) for further details on the edge connector. the processor socket connector is defined in this document is referred to as the 370-pin socket. see the 370-pin socket (pga370) design guidelines (order number 244410) for further details on the socket. 5.1 s.e.p. package this section defines the mechanical specifications and signal definitions for the intel ? celeron? processor in the s.e.p. package. 5.1.1 materials information the intel ? celeron? processor requires a retention mechanism. this retention mechanism may require motherboard hole dimensions to be 0.159" diameter holes if low cost plastic fasteners are used to secure the retention mechanisms in place. the larger diameter holes are necessary to provide a robust structural design that can guarantee stringent shock and vibe testing. if captive nuts are used in place of the plastic fasteners, then either the 0.159" or the 0.140" diameter holes will suffice as long as the corresponding sized attached mount is used. figure 14 with substrate dimensions is provided to aid in the design of a heat sink and clip. in figure 15 all area on the secondary side of the substrate is zoned keep out, except for 25 mils around the tooling holes and the top and side edges of the substrate.
46 datasheet intel ? celeron? processor 5.1.2 signal listing table 32 and table 33 provide the processor edge finger and sc242 connector signal definitions for intel ? celeron? processor. the signal locations on the sc242 edge connector are to be used for signal routing, simulation, and component placement on the motherboard. figure 14. intel ? celeron? processor substrate dimensions (s.e.p. package) figure 15. intel ? celeron? processor substrate primary/secondary side dimensions (s.e.p. package) -y- 1.660 .615 1.196 3.804 .814 .323 2.608 1.370 -y- 27.4 mm sr opening square 25.4 mm copper slug square -z- -y- .062 +.007 -.005 -e- -d- -g- -h- -e- -d- -g- -h- typ max. non-keepout area .025 typ max. non-keepout area .025 typ max. non-keepout area .025 typ max. non-keepout area .025 secondary side primary side there will be no components on secodonary side
datasheet 47 intel ? celeron? processor table 32. s.e.p. package signal listing by pin number pin no. pin name signal buffer type a1 v tt power/other a2 vss power/other a3 v tt power/other a4 ierr# cmos output a5 a20m# cmos input a6 vss power/other a7 ferr# cmos output a8 ignne# cmos input a9 tdi tap input a10 vss power/other a11 tdo tap output a12 pwrgood cmos input a13 testhi cmos test input a14 vss power/other a15 thermtrip# cmos output a16 reserved reserved for future use a17 lint0/intr cmos input a18 vss power/other a19 picd0 apic i/o a20 preq# cmos input a21 bp3# agtl+ i/o a22 vss power/other a23 bpm0# agtl+ i/o a24 reserved reserved for pentium ii processor a25 reserved reserved for pentium ii processor a26 vss power/other a27 reserved reserved for pentium ii processor a28 reserved reserved for pentium ii processor a29 reserved reserved for pentium ii processor a30 vss power/other a31 reserved reserved for pentium ii processor a32 d61# agtl+ i/o a33 d55# agtl+ i/o a34 vss power/other a35 d60# agtl+ i/o a36 d53# agtl+ i/o a37 d57# agtl+ i/o a38 vss power/other a39 d46# agtl+ i/o a40 d49# agtl+ i/o a41 d51# agtl+ i/o a42 vss power/other a43 d42# agtl+ i/o a44 d45# agtl+ i/o a45 d39# agtl+ i/o a46 vss power/other a47 reserved reserved for future use a48 d43# agtl+ i/o a49 d37# agtl+ i/o a50 vss power/other a51 d33# agtl+ i/o a52 d35# agtl+ i/o a53 d31# agtl+ i/o a54 vss power/other a55 d30# agtl+ i/o a56 d27# agtl+ i/o a57 d24# agtl+ i/o a58 vss power/other a59 d23# agtl+ i/o a60 d21# agtl+ i/o a61 d16# agtl+ i/o a62 vss power/other a63 d13# agtl+ i/o a64 d11# agtl+ i/o a65 d10# agtl+ i/o a66 vss power/other a67 d14# agtl+ i/o a68 d9# agtl+ i/o a69 d8# agtl+ i/o a70 vss power/other a71 d5# agtl+ i/o a72 d3# agtl+ i/o a73 d1# agtl+ i/o a74 vss power/other a75 bclk system bus clock input a76 reserved reserved for pentium ii processor table 32. s.e.p. package signal listing by pin number pin no. pin name signal buffer type
48 datasheet intel ? celeron? processor a77 reserved reserved for pentium ii processor a78 vss power/other a79 reserved reserved for pentium ii processor a80 reserved reserved for pentium ii processor a81 a30# agtl+ i/o a82 vss power/other a83 a31# agtl+ i/o a84 a27# agtl+ i/o a85 a22# agtl+ i/o a86 vss power/other a87 a23# agtl+ i/o a88 reserved reserved for future use a89 a19# agtl+ i/o a90 vss power/other a91 a18# agtl+ i/o a92 a16# agtl+ i/o a93 a13# agtl+ i/o a94 vss power/other a95 a14# agtl+ i/o a96 a10# agtl+ i/o a97 a5# agtl+ i/o a98 vss power/other a99 a9# agtl+ i/o a100 a4# agtl+ i/o a101 bnr# agtl+ i/o a102 vss power/other a103 bpri# agtl+ input a104 trdy# agtl+ input a105 defer# agtl+ input a106 vss power/other a107 req2# agtl+ i/o a108 req3# agtl+ i/o a109 hitm# agtl+ i/o a110 vss power/other a111 dbsy# agtl+ i/o a112 rs1# agtl+ input a113 reserved reserved for future use a114 vss power/other table 32. s.e.p. package signal listing by pin number pin no. pin name signal buffer type a115 ads# agtl+ i/o a116 reserved reserved for future use a117 reserved reserved for pentium ii processor a118 vss power/other a119 vid2 power/other a120 vid1 power/other a121 vid4 power/other b1 emi power/other b2 flush# cmos input b3 smi# cmos input b4 init# cmos input b5 v tt power/other b6 stpclk# cmos input b7 tck tap input b8 slp# cmos input b9 v tt power/other b10 tms tap input b13 v cc core power/other b14 thermdp power/other b15 thermdn power/other b16 lint1/nmi cmos input b17 v cc core power/other b18 picclk apic clock input b19 bp2# agtl+ i/o b20 reserved reserved for future use b21 bsel power/other b22 picd1 apic i/o b23 prdy# agtl+ output b24 bpm1# agtl+ i/o b25 v cc core power/other b26 reserved reserved for pentium ii processor b27 reserved reserved for pentium ii processor b28 reserved reserved for pentium ii processor b29 v cc core power/other b30 d62# agtl+ i/o b31 d58# agtl+ i/o b32 d63# agtl+ i/o b33 v cc core power/other table 32. s.e.p. package signal listing by pin number pin no. pin name signal buffer type
datasheet 49 intel ? celeron? processor b34 d56# agtl+ i/o b35 d50# agtl+ i/o b36 d54# agtl+ i/o b37 v cc core power/other b38 d59# agtl+ i/o b39 d48# agtl+ i/o b40 d52# agtl+ i/o b41 emi power/other b42 d41# agtl+ i/o b43 d47# agtl+ i/o b44 d44# agtl+ i/o b45 v cc core power/other b46 d36# agtl+ i/o b47 d40# agtl+ i/o b48 d34# agtl+ i/o b49 v cc core power/other b50 d38# agtl+ i/o b51 d32# agtl+ i/o b52 d28# agtl+ i/o b53 v cc core power/other b54 d29# agtl+ i/o b55 d26# agtl+ i/o b56 d25# agtl+ i/o b57 v cc core power/other b58 d22# agtl+ i/o b59 d19# agtl+ i/o b60 d18# agtl+ i/o b61 emi power/other b62 d20# agtl+ i/o b63 d17# agtl+ i/o b64 d15# agtl+ i/o b65 v cc core power/other b66 d12# agtl+ i/o b67 d7# agtl+ i/o b68 d6# agtl+ i/o b69 v cc core power/other b70 d4# agtl+ i/o b71 d2# agtl+ i/o b72 d0# agtl+ i/o b73 v cc core power/other table 32. s.e.p. package signal listing by pin number pin no. pin name signal buffer type b74 reset# agtl+ input b75 reserved reserved for future use b76 reserved reserved for future use b77 v cc core power/other b78 reserved reserved for pentium ii processor b79 reserved reserved for pentium ii processor b80 a29# agtl+ i/o b81 emi power/other b82 a26# agtl+ i/o b83 a24# agtl+ i/o b84 a28# agtl+ i/o b85 v cc core power/other b86 a20# agtl+ i/o b87 a21# agtl+ i/o b88 a25# agtl+ i/o b89 v cc core power/other b90 a15# agtl+ i/o b91 a17# agtl+ i/o b92 a11# agtl+ i/o b93 v cc core power/other b94 a12# agtl+ i/o b95 a8# agtl+ i/o b96 a7# agtl+ i/o b97 v cc core power/other b98 a3# agtl+ i/o b99 a6# agtl+ i/o b100 emi power/other b101 slotocc# power/other b102 req0# agtl+ i/o b103 req1# agtl+ i/o b104 req4# agtl+ i/o b105 v cc core power/other b106 lock# agtl+ i/o b107 drdy# agtl+ i/o b108 rs0# agtl+ input b109 v cc 5 power/other b11 trst# tap input b110 hit# agtl+ i/o b111 rs2# agtl+ input table 32. s.e.p. package signal listing by pin number pin no. pin name signal buffer type
50 datasheet intel ? celeron? processor b112 reserved reserved for future use b113 v cc l2 power/other. reserved for pentium ii processor b114 reserved reserved for pentium ii processor b115 reserved reserved for pentium ii processor b116 reserved reserved for pentium ii processor table 32. s.e.p. package signal listing by pin number pin no. pin name signal buffer type b117 v cc l2 power/other. reserved for pentium ii processor b118 reserved reserved for pentium ii processor b119 vid3 power/other b12 reserved reserved for future use b120 vid0 power/other b121 v cc l2 power/other. reserved for pentium ii processor table 32. s.e.p. package signal listing by pin number pin no. pin name signal buffer type
datasheet 51 intel ? celeron? processor table 33. s.e.p. package signal listing by signal name pin name pin no. signal buffer type a3# b98 agtl+ i/o a4# a100 agtl+ i/o a5# a97 agtl+ i/o a6# b99 agtl+ i/o a7# b96 agtl+ i/o a8# b95 agtl+ i/o a9# a99 agtl+ i/o a10# a96 agtl+ i/o a11# b92 agtl+ i/o a12# b94 agtl+ i/o a13# a93 agtl+ i/o a14# a95 agtl+ i/o a15# b90 agtl+ i/o a16# a92 agtl+ i/o a17# b91 agtl+ i/o a18# a91 agtl+ i/o a19# a89 agtl+ i/o a20# b86 agtl+ i/o a20m# a5 cmos input a21# b87 agtl+ i/o a22# a85 agtl+ i/o a23# a87 agtl+ i/o a24# b83 agtl+ i/o a25# b88 agtl+ i/o a26# b82 agtl+ i/o a27# a84 agtl+ i/o a28# b84 agtl+ i/o a29# b80 agtl+ i/o a30# a81 agtl+ i/o a31# a83 agtl+ i/o ads# a115 agtl+ i/o bclk a75 system bus clock input bnr# a101 agtl+ i/o bp2# b19 agtl+ i/o bp3# a21 agtl+ i/o bpm0# a23 agtl+ i/o bpm1# b24 agtl+ i/o bpri# a103 agtl+ input bsel b21 power/other d00# b72 agtl+ i/o d1# a73 agtl+ i/o d2# b71 agtl+ i/o d3# a72 agtl+ i/o d5# a71 agtl+ i/o d6# b68 agtl+ i/o d7# b67 agtl+ i/o d8# a69 agtl+ i/o d9# a68 agtl+ i/o d10# a65 agtl+ i/o d11# a64 agtl+ i/o d12# b66 agtl+ i/o d13# a63 agtl+ i/o d14# a67 agtl+ i/o d15# b64 agtl+ i/o d16# a61 agtl+ i/o d17# b63 agtl+ i/o d18# b60 agtl+ i/o d19# b59 agtl+ i/o d20# b62 agtl+ i/o d21# a60 agtl+ i/o d22# b58 agtl+ i/o d23# a59 agtl+ i/o d24# a57 agtl+ i/o d25# b56 agtl+ i/o d26# b55 agtl+ i/o d27# a56 agtl+ i/o d28# b52 agtl+ i/o d29# b54 agtl+ i/o d30# a55 agtl+ i/o d31# a53 agtl+ i/o d32# b51 agtl+ i/o d33# a51 agtl+ i/o d34# b48 agtl+ i/o d35# a52 agtl+ i/o table 33. s.e.p. package signal listing by signal name pin name pin no. signal buffer type
52 datasheet intel ? celeron? processor d36# b46 agtl+ i/o d37# a49 agtl+ i/o d38# b50 agtl+ i/o d39# a45 agtl+ i/o d4# b70 agtl+ i/o d40# b47 agtl+ i/o d41# b42 agtl+ i/o d42# a43 agtl+ i/o d43# a48 agtl+ i/o d44# b44 agtl+ i/o d45# a44 agtl+ i/o d46# a39 agtl+ i/o d47# b43 agtl+ i/o d48# b39 agtl+ i/o d49# a40 agtl+ i/o d50# b35 agtl+ i/o d51# a41 agtl+ i/o d52# b40 agtl+ i/o d53# a36 agtl+ i/o d54# b36 agtl+ i/o d55# a33 agtl+ i/o d56# b34 agtl+ i/o d57# a37 agtl+ i/o d58# b31 agtl+ i/o d59# b38 agtl+ i/o d60# a35 agtl+ i/o d61# a32 agtl+ i/o d62# b30 agtl+ i/o d63# b32 agtl+ i/o dbsy# a111 agtl+ i/o defer# a105 agtl+ input drdy# b107 agtl+ i/o emi b1 power/other emi b41 power/other emi b61 power/other emi b81 power/other emi b100 power/other table 33. s.e.p. package signal listing by signal name pin name pin no. signal buffer type ferr# a7 cmos output flush# b2 cmos input hit# b110 agtl+ i/o hitm# a109 agtl+ i/o ierr# a4 cmos output ignne# a8 cmos input init# b4 cmos input lint0/intr a17 cmos input lint1/nmi b16 cmos input lock# b106 agtl+ i/o picclk b18 apic clock input picd0 a19 apic i/o picd1 b22 apic i/o prdy# b23 agtl+ output preq# a20 cmos input pwrgood a12 cmos input req0# b102 agtl+ i/o req1# b103 agtl+ i/o req2# a107 agtl+ i/o req3# a108 agtl+ i/o req4# b104 agtl+ i/o reserved a16 reserved for future use reserved a47 reserved for future use reserved a77 reserved for pentium ii processor reserved a88 reserved for future use reserved a116 reserved for future use reserved b12 reserved for future use reserved a113 reserved for future use reserved b20 reserved for future use reserved b76 reserved for future use reserved b112 reserved for future use reserved b79 reserved for pentium ii processor reserved b114 reserved for pentium ii processor reserved b115 reserved for pentium ii processor table 33. s.e.p. package signal listing by signal name pin name pin no. signal buffer type
datasheet 53 intel ? celeron? processor reserved a117 reserved for pentium ii processor reserved b116 reserved for pentium ii processor reserved a24 reserved for pentium ii processor reserved a76 reserved for pentium ii processor reserved b75 reserved for future use reserved a79 reserved for pentium ii processor reserved a80 reserved for pentium ii processor reserved b78 reserved for pentium ii processor reserved b118 reserved for pentium ii processor reserved a25 reserved for pentium ii processor reserved a27 reserved for pentium ii processor reserved b26 reserved for pentium ii processor reserved a28 reserved for pentium ii processor reserved b27 reserved for pentium ii processor reserved a29 reserved for pentium ii processor reserved a31 reserved for pentium ii processor reserved b28 reserved for pentium ii processor reset# b74 agtl+ input rs0# b108 agtl+ input rs1# a112 agtl+ input rs2# b111 agtl+ input slotocc# b101 power/other slp# b8 cmos input smi# b3 cmos input stpclk# b6 cmos input tck b7 tap input tdi a9 tap input tdo a11 tap output table 33. s.e.p. package signal listing by signal name pin name pin no. signal buffer type testhi a13 cmos test input thermdn b15 power/other thermdp b14 power/other thermtrip# a15 cmos output tms b10 tap input trdy# a104 agtl+ input trst# b11 tap input v cc 5 b109 power/other v cc core b13 power/other v cc core b17 power/other v cc core b25 power/other v cc core b29 power/other v cc core b33 power/other v cc core b37 power/other v cc core b45 power/other v cc core b49 power/other v cc core b53 power/other v cc core b57 power/other v cc core b65 power/other v cc core b69 power/other v cc core b73 power/other v cc core b77 power/other v cc core b85 power/other v cc core b89 power/other v cc core b93 power/other v cc core b97 power/other v cc core b105 power/other v cc l2 b113 power/other. reserved for pentium ii processor v cc l2 b117 power/other. reserved for pentium ii processor v cc l2 b121 power/other. reserved for pentium ii processor vid0 b120 power/other vid1 a120 power/other vid2 a119 power/other vid3 b119 power/other vid4 a121 power/other vss a114 power/other table 33. s.e.p. package signal listing by signal name pin name pin no. signal buffer type
54 datasheet intel ? celeron? processor vss a118 power/other vss a46 power/other vss a38 power/other vss a42 power/other vss a50 power/other vss a54 power/other vss a58 power/other vss a62 power/other vss a66 power/other vss a70 power/other vss a74 power/other vss a78 power/other vss a82 power/other vss a86 power/other vss a2 power/other vss a6 power/other table 33. s.e.p. package signal listing by signal name pin name pin no. signal buffer type vss a10 power/other vss a14 power/other vss a18 power/other vss a22 power/other vss a26 power/other vss a30 power/other vss a34 power/other vss a98 power/other vss a102 power/other vss a106 power/other vss a110 power/other v tt a1 power/other v tt a3 power/other v tt b5 power/other v tt b9 power/other table 33. s.e.p. package signal listing by signal name pin name pin no. signal buffer type
datasheet 55 intel ? celeron? processor 5.2 ppga package this section defines the mechanical specifications and signal definitions for the intel ? celeron? processor in the ppga package. 5.2.1 materials information figure 16 and table 34 are provided to aid in the design of a heat sink and clip. figure 16. ppga package dimensions d1 d d s1 b1 b2 heat slug solder resist d2 a1 l seating plane e1 f b a a2 side view bottom view top view 45 x 0.085
56 datasheet intel ? celeron? processor table 34. ppga package dimensions millimeters inches symbol min max notes min max notes a 1.83 2.23 0.072 0.088 a 1 1.00 0.039 a 2 2.72 3.33 0.107 0.131 b 0.40 0.51 0.016 0.020 d 49.43 49.63 1.946 1.954 d 1 45.59 45.85 1.795 1.805 d 2 25.15 25.65 0.099 1.010 e 1 2.29 2.79 0.090 0.110 l 3.05 3.30 0.120 0.130 n 370 lead count 370 lead count s 1 1.52 2.54 0.060 0.100 table 35. ppga package information summary package type total pins pin array package size plastic staggered pin grid array (ppga) 370 37 x 37 1.95" x 1.95" 4.95 cm x 4.95 cm
datasheet 57 intel ? celeron? processor 5.2.2 signal listing figure 17. ppga package (pin side view) a13# a16# an am al ak aj ah ag af ae ad ac ab aa z y x w v u t s r q p n m l k j h g f e d c b a vss vcc vss d35# d29# d33# d26# d28# d21# d23# d25# vss vcc vss d31# vcc d43# vcc vss d34# d38# vcc vss d39# d36# vcc d37# d44# vcc vcc d32# d22# rsvd d27# vss d42# d45# d49# vss vcc d63# vref1 vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss v core det rsvd d62# rsvd rsvd rsvd vref0 bpm1# bp3# d41# d52# vss vcc vss vcc vss vcc vss vcc vss vcc d40# d59# d55# d54# d58# d50# d56# rsvd rsvd rsvd bpm0# cpupres# vcc vss vcc vss vcc vss vcc vss vcc vss vcc rsvd d51# d47# d48# d57# d46# d53# d60# d61# rsvd rsvd rsvd prdy# vss bp2# rsvd rsvd vcc vss vcc picclk picd0 preq# vcc vcc vss rsvd picd1 lint1 vcc vss lint0 rsvd rsvd rsvd vss vcc vss rsvd rsvd rsvd vcc vss vcc rsvd rsvd rsvd vss vcc vss pll2 rsvd rsvd vcc vss vcc vss vcc vss vcc vss v2.5 rsvd rsvd vcc vss vcc vcmos vss ferr# rsvd vcc vss v1.5 a20m# ierr# flush# vss vcc vss init# vss vcc vss pll1 rsvd bclk stpclk# ignne# vss d16# d19# d7# d30# vcc vcc vref2 d24# d13# d20# vss vss d11# d3# d2# d14# vcc vcc d18# d9# d12# d10# vss rsvd d17# vref3 d8# d5# vcc vcc d1# d6# d4# d15# vss vss rsvd vref4 d0# rsvd vcc rsvd reset# rsvd rsvd a26# vss vss a29# a18# a27# a30# vcc vcc a24# a23# rsvd a20# vss vss a31# vref5 a17# a22# vcc vcc rsvd a25# edgctrl a19# vss vss rsvd a10# a5# a8# a4# bnr# req1# req2# rsvd rs1# vcc rs0# thermtrip# slp# vcc vss vcc a21# vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss bsel# smi# vid3 vcc vss a28# a3# a11# vref6 a14# rsvd req0# lock# vref7 rsvd pwrgd rs2# rsvd tms vcc vss vss vss a15# a9# rsvd rsvd a7# req4# req3# rsvd hitm# hit# dbsy# thrmdn thrmdp tck vid0 vid2 vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vid1 vss a12# a6# rsvd rsvd rsvd bpri# defer# rsvd rsvd trdy# drdy# br0# ads# trst# tdi tdo an am al ak aj ah ag af ae ad ac ab aa z y x w v u t s r q p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10111213141516171819202122 23 24252627282930313233 34353637 1 2 3 4 5 6 7 8 9 10111213141516171819202122 23 24252627282930313233 34353637
58 datasheet intel ? celeron? processor table 36. ppga package signal listing by pin number pin no. pin name signal buffer type a3 d29# agtl+ i/o a5 d28# agtl+ i/o a7 d43# agtl+ i/o a9 d37# agtl+ i/o a11 d44# agtl+ i/o a13 d51# agtl+ i/o a15 d47# agtl+ i/o a17 d48# agtl+ i/o a19 d57# agtl+ i/o a21 d46# agtl+ i/o a23 d53# agtl+ i/o a25 d60# agtl+ i/o a27 d61# agtl+ i/o a29 reserved reserved for future use a31 reserved reserved for future use a33 reserved reserved for future use a35 prdy# agtl+ output a37 vss power/other aa1 a27# agtl+ i/o aa3 a30# agtl+ i/o aa5 v cc core power/other aa33 reserved reserved for future use aa35 reserved reserved for future use aa37 v cc core power/other ab2 v cc core power/other ab4 a24# agtl+ i/o ab6 a23# agtl+ i/o ab32 vss power/other ab34 v cc core power/other ab36 v cc cmos power/other ac1 reserved reserved for future use ac3 a20# agtl+ i/o ac5 vss power/other ac33 vss power/other ac35 ferr# cmos output ac37 reserved reserved for future use ad2 vss power/other ad4 a31# agtl+ i/o ad6 v ref 5 power/other ad32 v cc core power/other ad34 vss power/other ad36 v cc 1.5 power/other ae1 a17# agtl+ i/o ae3 a22# agtl+ i/o ae5 v cc core power/other ae33 a20m# cmos input ae35 ierr# cmos output ae37 flush# cmos input af2 v cc core power/other af4 reserved reserved for future use af6 a25# agtl+ i/o af32 vss power/other af34 v cc core power/other af36 vss power/other ag1 edgctrl power/other ag3 a19# agtl+ i/o ag5 vss power/other ag33 init# cmos input ag35 stpclk# cmos input ag37 ignne# cmos input ah2 vss power/other ah4 reserved reserved for future use ah6 a10# agtl+ i/o ah8 a5# agtl+ i/o ah10 a8# agtl+ i/o ah12 a4# agtl+ i/o ah14 bnr# agtl+ i/o ah16 req1# agtl+ i/o ah18 req2# agtl+ i/o ah20 reserved reserved for future use ah22 rs1# agtl+ input ah24 v cc core power/other ah26 rs0# agtl+ input ah28 thermtri p# cmos output table 36. ppga package signal listing by pin number pin no. pin name signal buffer type
datasheet 59 intel ? celeron? processor ah30 slp# cmos input ah32 v cc core power/other ah34 vss power/other ah36 v cc core power/other aj01 a21# agtl+ i/o aj03 vss power/other aj05 v cc core power/other aj07 vss power/other aj09 v cc core power/other aj11 vss power/other aj13 v cc core power/other aj15 vss power/other aj17 v cc core power/other aj19 vss power/other aj21 v cc core power/other aj23 vss power/other aj25 v cc core power/other aj27 vss power/other aj29 v cc core power/other aj31 vss power/other aj33 bsel power/other aj35 smi# cmos input aj37 vid3 power/other ak02 v cc core power/other ak04 vss power/other ak06 a28# agtl+ i/o ak08 a3# agtl+ i/o ak10 a11# agtl+ i/o ak12 v ref 6 power/other ak14 a14# agtl+ i/o ak16 reserved reserved for future use ak18 req0# agtl+ i/o ak20 lock# agtl+ i/o ak22 v ref 7 power/other ak24 reserved reserved for future use ak26 pwrgood cmos input ak28 rs2# agtl+ input ak30 reserved reserved for future use table 36. ppga package signal listing by pin number pin no. pin name signal buffer type ak32 tms tap input ak34 v cc core power/other ak36 vss power/other al01 vss power/other al03 vss power/other al05 a15# agtl+ i/o al07 a13# agtl+ i/o al09 a9# agtl+ i/o al11 reserved reserved for future use al13 reserved reserved for future use al15 a7# agtl+ i/o al17 req4# agtl+ i/o al19 req3# agtl+ i/o al21 reserved reserved for future use al23 hitm# agtl+ i/o al25 hit# agtl+ i/o al27 dbsy# agtl+ i/o al29 thermdn power/other al31 thermdp power/other al33 tck tap input al35 vid0 voltage identification al37 vid2 voltage identification am04 v cc core power/other am06 vss power/other am08 v cc core power/other am10 vss power/other am12 v cc core power/other am14 vss power/other am16 v cc core power/other am18 vss power/other am2 vss power/other am20 v cc core power/other am22 vss power/other am24 v cc core power/other am26 vss power/other am28 v cc core power/other am30 vss power/other am32 v cc core power/other table 36. ppga package signal listing by pin number pin no. pin name signal buffer type
60 datasheet intel ? celeron? processor am34 vss power/other am36 vid1 voltage identification an3 vss power/other an5 a12# agtl+ i/o an7 a16# agtl+ i/o an9 a6# agtl+ i/o an11 reserved reserved for future use an13 reserved reserved for future use an15 reserved reserved for future use an17 bpri# agtl+ input an19 defer# agtl+ input an21 reserved reserved for future use an23 reserved reserved for future use an25 trdy# agtl+ input an27 drdy# agtl+ i/o an29 br0# agtl+ i/o an31 ads# agtl+ i/o an33 trst# tap input an35 tdi tap input an37 tdo tap output b2 d35# agtl+ i/o b4 vss power/other b6 v cc core power/other b8 vss power/other b10 v cc core power/other b12 vss power/other b14 v cc core power/other b16 vss power/other b18 v cc core power/other b20 vss power/other b22 v cc core power/other b24 vss power/other b26 v cc core power/other b28 vss power/other b30 v cc core power/other b32 vss power/other b34 v cc core power/other b36 reserved reserved for future use table 36. ppga package signal listing by pin number pin no. pin name signal buffer type c1 d33# agtl+ i/o c3 v cc core power/other c5 d31# agtl+ i/o c7 d34# agtl+ i/o c9 d36# agtl+ i/o c11 d45# agtl+ i/o c13 d49# agtl+ i/o c15 d40# agtl+ i/o c17 d59# agtl+ i/o c19 d55# agtl+ i/o c21 d54# agtl+ i/o c23 d58# agtl+ i/o c25 d50# agtl+ i/o c27 d56# agtl+ i/o c29 reserved reserved for future use c31 reserved reserved for future use c33 reserved reserved for future use c35 bpm0# agtl+ i/o c37 cpupres# power/other d2 vss power/other d4 vss power/other d6 v cc core power/other d8 d38# agtl+ i/o d10 d39# agtl+ i/o d12 d42# agtl+ i/o d14 d41# agtl+ i/o d16 d52# agtl+ i/o d18 vss power/other d20 v cc core power/other d22 vss power/other d24 v cc core power/other d26 vss power/other d28 v cc core power/other d30 vss power/other d32 v cc core power/other d34 vss power/other d36 v cc core power/other e1 d26# agtl+ i/o table 36. ppga package signal listing by pin number pin no. pin name signal buffer type
datasheet 61 intel ? celeron? processor e3 d25# agtl+ i/o e5 v cc core power/other e7 vss power/other e9 v cc core power/other e11 vss power/other e13 v cc core power/other e15 vss power/other e17 v cc core power/other e19 vss power/other e21 v core det power/other e23 reserved power/other e25 d62# power/other e27 reserved reserved for future use e29 reserved reserved for future use e31 reserved reserved for future use e33 v ref 0 power/other e35 bpm1# agtl+ i/o e37 bp3# agtl+ i/o f2 v cc core power/other f4 v cc core power/other f6 d32# agtl+ i/o f8 d22# agtl+ i/o f10 reserved reserved for future use f12 d27# agtl+ i/o f14 v cc core power/other f16 d63# agtl+ i/o f18 v ref 1 power/other f20 vss power/other f22 v cc core power/other f24 vss power/other f26 v cc core power/other f28 vss power/other f30 v cc core power/other f32 vss power/other f34 v cc core power/other f36 vss power/other g1 d21# agtl+ i/o g3 d23# agtl+ i/o table 36. ppga package signal listing by pin number pin no. pin name signal buffer type g5 vss power/other g33 bp2# agtl+ i/o g35 reserved reserved for future use g37 reserved reserved for future use h2 vss power/other h4 d16# agtl+ i/o h6 d19# agtl+ i/o h32 v cc core power/other h34 vss power/other h36 v cc core power/other j1 d7# agtl+ i/o j3 d30# agtl+ i/o j5 v cc core power/other j33 picclk apic clock input j35 picd0 apic i/o j37 preq# cmos input k2 v cc core power/other k4 v ref 2 power/other k6 d24# agtl+ i/o k32 v cc core power/other k34 v cc core power/other k36 vss power/other l1 d13# agtl+ i/o l3 d20# agtl+ i/o l5 vss power/other l33 reserved reserved for future use l35 picd1 apic i/o l37 lint1/nmi cmos input m2 vss power/other m4 d11# agtl+ i/o m6 d3# agtl+ i/o m32 v cc core power/other m34 vss power/other m36 lint0/intr cmos input n1 d2# agtl+ i/o n3 d14# agtl+ i/o n5 v cc core power/other n33 reserved reserved for future use table 36. ppga package signal listing by pin number pin no. pin name signal buffer type
62 datasheet intel ? celeron? processor n35 reserved reserved for future use n37 reserved reserved for future use p2 v cc core power/other p4 d18# agtl+ i/o p6 d9# agtl+ i/o p32 vss power/other p34 v cc core power/other p36 vss power/other q1 d12# agtl+ i/o q3 d10# agtl+ i/o q5 vss power/other q33 reserved reserved for future use q35 reserved reserved for future use q37 reserved reserved for future use r2 reserved reserved for future use r4 d17# agtl+ i/o r6 v ref 3 power/other r32 v cc core power/other r34 vss power/other r36 v cc core power/other s1 d8# agtl+ i/o s3 d5# agtl+ i/o s5 v cc core power/other s33 reserved reserved for future use s35 reserved reserved for future use s37 reserved reserved for future use t2 v cc core power/other t4 d1# agtl+ i/o t6 d6# agtl+ i/o t32 vss power/other t34 v cc core power/other t36 vss power/other u1 d4# agtl+ i/o u3 d15# agtl+ i/o table 36. ppga package signal listing by pin number pin no. pin name signal buffer type u5 vss power/other u33 pll2 power/other u35 reserved reserved for future use u37 reserved reserved for future use v2 vss power/other v4 reserved reserved for future use v6 v ref 4 power/other v32 v cc core power/other v34 vss power/other v36 v cc core power/other w1 d0# agtl+ i/o w3 reserved reserved for future use w5 v cc core power/other w33 pll1 power/other w35 reserved reserved for future use w37 bclk system bus clock input x2 reserved reserved for future use x4 reset# agtl+ input x6 reserved reserved for future use x32 vss power/other x34 v cc core power/other x36 vss power/other y1 reserved reserved for future use y3 a26# agtl+ i/o y5 vss power/other y33 vss power/other y35 v cc core power/other y37 vss power/other z2 vss power/other z4 a29# agtl+ i/o z6 a18# agtl+ i/o z32 v cc core power/other z34 vss power/other z36 v cc 2.5 power/other table 36. ppga package signal listing by pin number pin no. pin name signal buffer type
datasheet 63 intel ? celeron? processor table 37. ppga package signal listing in order by signal name pin name pin no. signal buffer type a3# ak8 agtl+ i/o a4# ah12 agtl+ i/o a5# ah8 agtl+ i/o a6# an9 agtl+ i/o a7# al15 agtl+ i/o a8# ah10 agtl+ i/o a9# al9 agtl+ i/o a10# ah6 agtl+ i/o a11# ak10 agtl+ i/o a12# an5 agtl+ i/o a13# al7 agtl+ i/o a14# ak14 agtl+ i/o a15# al5 agtl+ i/o a16# an7 agtl+ i/o a17# ae1 agtl+ i/o a18# z6 agtl+ i/o a19# ag3 agtl+ i/o a20# ac3 agtl+ i/o a21# aj1 agtl+ i/o a22# ae3 agtl+ i/o a23# ab6 agtl+ i/o a24# ab4 agtl+ i/o a25# af6 agtl+ i/o a26# y3 agtl+ i/o a27# aa1 agtl+ i/o a28# ak6 agtl+ i/o a29# z4 agtl+ i/o a30# aa3 agtl+ i/o a31# ad4 agtl+ i/o a20m# ae33 cmos input ads# an31 agtl+ i/o bclk w37 system bus clock input bnr# ah14 agtl+ i/o bp2# g33 agtl+ i/o bp3# e37 agtl+ i/o bpm0# c35 agtl+ i/o bpm1# e35 agtl+ i/o bpri# an17 agtl+ input br0# an29 agtl+ i/o bsel aj33 power/other cpupres# c37 power/other d0# w1 agtl+ i/o d1# t4 agtl+ i/o d2# n1 agtl+ i/o d3# m6 agtl+ i/o d4# u1 agtl+ i/o d5# s3 agtl+ i/o d6# t6 agtl+ i/o d7# j1 agtl+ i/o d8# s1 agtl+ i/o d9# p6 agtl+ i/o d10# q3 agtl+ i/o d11# m4 agtl+ i/o d12# q1 agtl+ i/o d13# l1 agtl+ i/o d14# n3 agtl+ i/o d15# u3 agtl+ i/o d16# h4 agtl+ i/o d17# r4 agtl+ i/o d18# p4 agtl+ i/o d19# h6 agtl+ i/o d20# l3 agtl+ i/o d21# g1 agtl+ i/o d22# f8 agtl+ i/o d23# g3 agtl+ i/o d24# k6 agtl+ i/o d25# e3 agtl+ i/o d26# e1 agtl+ i/o d27# f12 agtl+ i/o d28# a5 agtl+ i/o d29# a3 agtl+ i/o d30# j3 agtl+ i/o d31# c5 agtl+ i/o d32# f6 agtl+ i/o d33# c1 agtl+ i/o d34# c7 agtl+ i/o d35# b2 agtl+ i/o d36# c9 agtl+ i/o d37# a9 agtl+ i/o d38# d8 agtl+ i/o table 37. ppga package signal listing in order by signal name pin name pin no. signal buffer type
64 datasheet intel ? celeron? processor d39# d10 agtl+ i/o d40# c15 agtl+ i/o d41# d14 agtl+ i/o d42# d12 agtl+ i/o d43# a7 agtl+ i/o d44# a11 agtl+ i/o d45# c11 agtl+ i/o d46# a21 agtl+ i/o d47# a15 agtl+ i/o d48# a17 agtl+ i/o d49# c13 agtl+ i/o d50# c25 agtl+ i/o d51# a13 agtl+ i/o d52# d16 agtl+ i/o d53# a23 agtl+ i/o d54# c21 agtl+ i/o d55# c19 agtl+ i/o d56# c27 agtl+ i/o d57# a19 agtl+ i/o d58# c23 agtl+ i/o d59# c17 agtl+ i/o d60# a25 agtl+ i/o d61# a27 agtl+ i/o d62# e25 agtl+ i/o d63# f16 agtl+ i/o dbsy# al27 agtl+ i/o defer# an19 agtl+ input drdy# an27 agtl+ i/o edgctrl ag1 power/other ferr# ac35 cmos output flush# ae37 cmos input hit# al25 agtl+ i/o hitm# al23 agtl+ i/o ierr# ae35 cmos output ignne# ag37 cmos input init# ag33 cmos input lint0/intr m36 cmos input lint1/nmi l37 cmos input lock# ak20 agtl+ i/o picclk j33 apic clock input table 37. ppga package signal listing in order by signal name pin name pin no. signal buffer type picd0 j35 apic i/o picd1 l35 apic i/o pll1 w33 power/other pll2 u33 power/other prdy# a35 agtl+ output preq# j37 cmos input pwrgood ak26 cmos input req0# ak18 agtl+ i/o req1# ah16 agtl+ i/o req2# ah18 agtl+ i/o req3# al19 agtl+ i/o req4# al17 agtl+ i/o reserved ac1 reserved for future use reserved ac37 reserved for future use reserved af4 reserved for future use reserved ak16 reserved for future use reserved ak24 reserved for future use reserved ak30 reserved for future use reserved al11 reserved for future use reserved al13 reserved for future use reserved al21 reserved for future use reserved an11 reserved for future use reserved an13 reserved for future use reserved an15 reserved for future use reserved an21 reserved for future use reserved an23 reserved for future use reserved b36 reserved for future use reserved c29 reserved for future use reserved c31 reserved for future use reserved c33 reserved for future use reserved e23 reserved for future use reserved e29 reserved for future use reserved e31 reserved for future use reserved f10 reserved for future use reserved g35 reserved for future use reserved g37 reserved for future use reserved l33 reserved for future use reserved n33 reserved for future use reserved n35 reserved for future use reserved n37 reserved for future use table 37. ppga package signal listing in order by signal name pin name pin no. signal buffer type
datasheet 65 intel ? celeron? processor reserved q33 reserved for future use reserved q35 reserved for future use reserved q37 reserved for future use reserved s33 reserved for future use reserved s37 reserved for future use reserved u35 reserved for future use reserved u37 reserved for future use reserved v4 reserved for future use reserved w3 reserved for future use reserved w35 reserved for future use reserved ah20 reserved for future use reserved ah4 reserved for future use reserved a29 reserved for future use reserved a31 reserved for future use reserved a33 reserved for future use reserved aa33 reserved for future use reserved aa35 reserved for future use reserved x6 reserved for future use reserved y1 reserved for future use reserved e27 reserved for future use reserved r2 reserved for future use reserved s35 reserved for future use reserved x2 reserved for future use reset# x4 agtl+ input rs0# ah26 agtl+ input rs1# ah22 agtl+ input rs2# ak28 agtl+ input slp# ah30 cmos input smi# aj35 cmos input stpclk# ag35 cmos input tck al33 tap input tdi an35 tap input tdo an37 tap output thermdn al29 power/other thermdp al31 power/other thermtrip# ah28 cmos output tms ak32 tap input trdy# an25 agtl+ input trst# an33 tap input v cc 1.5 ad36 power/other table 37. ppga package signal listing in order by signal name pin name pin no. signal buffer type v cc 2.5 z36 power/other v cc cmos ab36 power/other v cc core aj25 power/other v cc core aj29 power/other v cc core aj5 power/other v cc core aj9 power/other v cc core ak2 power/other v cc core ak34 power/other v cc core am12 power/other v cc core am16 power/other v cc core am20 power/other v cc core am24 power/other v cc core am28 power/other v cc core am32 power/other v cc core am4 power/other v cc core am8 power/other v cc core b10 power/other v cc core b14 power/other v cc core b18 power/other v cc core b22 power/other v cc core b26 power/other v cc core b30 power/other v cc core b34 power/other v cc core b6 power/other v cc core c3 power/other v cc core d20 power/other v cc core d24 power/other v cc core d28 power/other v cc core d32 power/other v cc core d36 power/other v cc core d6 power/other v cc core e13 power/other v cc core e17 power/other v cc core e5 power/other v cc core e9 power/other v cc core f14 power/other v cc core f2 power/other v cc core f22 power/other v cc core f26 power/other v cc core aa37 power/other table 37. ppga package signal listing in order by signal name pin name pin no. signal buffer type
66 datasheet intel ? celeron? processor v cc core aa5 power/other v cc core ab2 power/other v cc core ab34 power/other v cc core ad32 power/other v cc core ae5 power/other v cc core af2 power/other v cc core af34 power/other v cc core ah24 power/other v cc core ah32 power/other v cc core ah36 power/other v cc core aj13 power/other v cc core aj17 power/other v cc core aj21 power/other v cc core f30 power/other v cc core f34 power/other v cc core f4 power/other v cc core h32 power/other v cc core h36 power/other v cc core j5 power/other v cc core k2 power/other v cc core k32 power/other v cc core k34 power/other v cc core m32 power/other v cc core n5 power/other v cc core p2 power/other v cc core p34 power/other v cc core r32 power/other v cc core r36 power/other v cc core s5 power/other v cc core t2 power/other v cc core t34 power/other v cc core v32 power/other v cc core v36 power/other v cc core w5 power/other v cc core x34 power/other v cc core y35 power/other v cc core z32 power/other v core det e21 power/other vid0 al35 power/other vid1 am36 power/other table 37. ppga package signal listing in order by signal name pin name pin no. signal buffer type vid2 al37 power/other vid3 aj37 power/other v ref 0 e33 power/other v ref 1 f18 power/other v ref 2 k4 power/other v ref 3 r6 power/other v ref 4 v6 power/other v ref 5 ad6 power/other v ref 6 ak12 power/other v ref 7 ak22 power/other vss b16 power/other vss b20 power/other vss b24 power/other vss b28 power/other vss b32 power/other vss b4 power/other vss b8 power/other vss d18 power/other vss d2 power/other vss d22 power/other vss d26 power/other vss d30 power/other vss d34 power/other vss d4 power/other vss e11 power/other vss e15 power/other vss e19 power/other vss e7 power/other vss f20 power/other vss f24 power/other vss f28 power/other vss f32 power/other vss f36 power/other vss g5 power/other vss h2 power/other vss h34 power/other vss k36 power/other vss l5 power/other vss m2 power/other vss m34 power/other table 37. ppga package signal listing in order by signal name pin name pin no. signal buffer type
datasheet 67 intel ? celeron? processor vss p32 power/other vss p36 power/other vss q5 power/other vss r34 power/other vss t32 power/other vss t36 power/other vss u5 power/other vss v2 power/other vss a37 power/other vss ab32 power/other vss ac33 power/other vss ac5 power/other vss ad2 power/other vss ad34 power/other vss af32 power/other vss af36 power/other vss ag5 power/other vss ah2 power/other vss ah34 power/other vss aj11 power/other vss aj15 power/other vss aj19 power/other vss aj23 power/other vss aj27 power/other vss aj3 power/other table 37. ppga package signal listing in order by signal name pin name pin no. signal buffer type vss aj7 power/other vss ak36 power/other vss ak4 power/other vss al1 power/other vss al3 power/other vss am10 power/other vss am14 power/other vss am18 power/other vss am2 power/other vss am22 power/other vss am26 power/other vss am30 power/other vss am34 power/other vss am6 power/other vss an3 power/other vss b12 power/other vss v34 power/other vss x32 power/other vss x36 power/other vss y37 power/other vss y5 power/other vss z2 power/other vss z34 power/other vss aj31 power/other vss y33 power/other table 37. ppga package signal listing in order by signal name pin name pin no. signal buffer type
68 datasheet intel ? celeron? processor 5.3 heat sink volumetric keepout zone guidelines when designing a system platform it is necessary to ensure sufficient space is left for a heat sink to be installed without mechanical interference. due to the large number of proprietary heat sink designs, intel cannot specify a keepout zone that covers all passive and active-fan heat sinks. it is the system designers responsibility to consider their own proprietary solution when designing the desired keepout zone in their system platform. please refer to the intel ? celeron? processor (ppga) at 466 mhz thermal solutions guidelines (order number 245156) for further guidance. note: the heat sink keepout zones found in section 6.0, boxed processor specifications on page 68 refer specifically to the boxed processors active-fan heat sink. this does not reflect the worst-case dimensions that may exist with other third party passive or active-fan heat sinks. contact your vendor of choice for their passive or active-fan heat sink dimensions to ensure that mechanical interference with system platform components does not occur. 6.0 boxed processor specifications 6.1 s.e.p. package 6.1.1 introduction the intel ? celeron? processor is also offered as an intel boxed processor in the s.e.p. package at the following processor speeds: 400 mhz, 366 mhz, 333 mhz, 300a mhz, 300 mhz, and 266 mhz. intel boxed processors are intended for system integrators who build systems from motherboards and standard components. the boxed intel celeron processor in the s.e.p. package will be supplied with an attached fan heat sink. this section documents motherboard and system requirements for the fan heat sink that will be supplied with the boxed intel celeron processor. this section is particularly important for oems that manufacture motherboards for system integrators. unless otherwise noted, all figures in this section are dimensioned in inches. figure 18 shows a mechanical representation of the boxed intel celeron processor in a s.e.p. package in the retention mechanism, which is not shipped with the boxed intel celeron processor. note that the airflow of the fan heat sink is into the center and out of the sides of the fan heat sink. note: the heat sink keepout zones found in this section refer specifically to the boxed processors active- fan heat sink. this does not reflect the worst-case dimensions that may exist with other third party passive or active-fan heat sinks. contact your vendor of choice for their passive or active-fan heat sink dimensions to ensure that mechanical interference with system platform components does not occur.
datasheet 69 intel ? celeron? processor 6.1.2 mechanical specifications this section documents the mechanical specifications of the boxed intel ? celeron? processor fan heat sink. the boxed processor ships with an attached fan heat sink. clearance is required around the fan heat sink to ensure unimpeded airflow for proper cooling. the space requirements and dimensions for the boxed processor with integrated fan heat sink are shown in figure 19 , figure 20 , and figure 21 . all dimensions are in inches. note that these drawings show a conceptual attachment interface to a s.e.p. package low profile retention mechanism. figure 18. boxed intel ? celeron? processor in s.e.p. package in the retention mechanism figure 19. side view space requirements for the boxed processor 242-contact slot connector fan heatsin k s.e.p.p. 1.386 (a) 0.576 (b)
70 datasheet intel ? celeron? processor 6.1.2.1 boxed processor heat sink dimensions note: drawings reflect only the specifications of the intel boxed processor product. these dimensions should not be used as a universal keepout zone that covers all heat sinks. it is the system designers responsibility to consider their own proprietary solution when designing the desired keepout zone in their system platform. figure 20. front view space requirements for the boxed processor figure 21. top view airspace requirements for the boxed processor table 38. boxed processor fan heat sink spatial dimensions fig. ref. label dimensions (inches) min typ max a fan heat sink depth (see figure 19 ) 1.386 b fan heat sink height from motherboard (see figure 19 ) 0.576 c fan heat sink height (see figure 20 )2.02 d fan heat sink width (see figure 20 )4.74 e fan heat sink base width (see figure 20 )5.40 f airflow keepout zones from end of fan heat sink 0.40 g airflow keepout zones from face of fan heat sink 0.20 4.74 (d) 2.02 (c) 5.40 (e) 0.40 min air space (f) (both ends) 0.20 min air space (g) measure ambient temperature 0.3" above center of fan inlet fan heatsink processor airspace
datasheet 71 intel ? celeron? processor 6.1.2.2 boxed processor heat sink weight the boxed processor heat sink will not weigh more than 225 grams. 6.1.2.3 boxed processor retention mechanism the boxed intel ? celeron? processor requires a s.e.p. package retention mechanism to secure the processor in the sc242 connector. a s.e.p. package retention mechanism will not be provided with the boxed processor. motherboards designed for use by system integrators should include a retention mechanism and appropriate installation instructions. the boxed intel celeron processor does not require additional fan heat sink supports. fan heat sink supports will not be shipped with the boxed intel celeron processor. motherboards designed for flexible use by system integrators must still recognize the boxed pentium ii processors fan heat sink clearance requirements, which are described in the pentium ? ii processor at 233, 266, 300, and 333 mhz datasheet (order number 243335). 6.1.3 boxed processor requirements the boxed processor's fan heat sink requires a +12 v power supply. a fan power cable is shipped with the boxed processor to draw power from a power header on the motherboard. the power cable connector and pin-out are shown in figure 22 . motherboards must provide a matched power header to support the boxed processor. table 39 contains specifications for the input and output signals at the fan heat sink connector. the cable length is 7.0 inches ( 0.25"). the fan heat sink outputs a sense signal, which is an open-collector output, that pulses at a rate of two pulses per fan revolution. a motherboard pull-up resistor provides voh to match the motherboard-mounted fan speed monitor requirements, if applicable. use of the sense signal is optional. if the sense signal is not used, pin 3 of the connector should be tied to gnd. the power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. the power header identification and location should be documented in the motherboard documentation or on the motherboard. figure 23 shows the recommended location of the fan power connector relative to the sc242 connector. the motherboard power header should be positioned within 4.75 inches (lateral) of the fan power connector. figure 22. boxed processor fan heat sink power cable connector description pin signal straight square pin, 3-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pin pitch, 0.025" square pin width. waldom*/molex* p/n 22-01-3037 or equivalent. match with straight pin, friction lock header on motherboard waldom/molex p/n 22-23-2031, amp* p/n 640456-3, or equivalent. 1 2 3 gnd +12v sense 12 3
72 datasheet intel ? celeron? processor 6.1.4 thermal specifications this section describes the cooling requirements of the fan heat sink solution utilized by the boxed processor. 6.1.4.1 boxed processor cooling requirements the boxed processor is cooled with a fan heat sink. the boxed processor fan heat sink will keep the processor core case temperature, t case , within the specifications (see table 27 ), provided airflow through the fan heat sink is unimpeded and the air temperature entering the fan is below 45 c (see figure 21 for measurement location). airspace is required around the fan to ensure that the airflow through the fan heat sink is not blocked. blocking the airflow to the fan heat sink reduces the cooling efficiency and decreases fan life. figure 21 illustrates an acceptable airspace clearance for the fan heat sink. table 39. fan heat sink power and signal specifications description min typ max +12 v: 12 volt fan power supply 7 v 12 v 13.8 v ic: fan current draw 100 ma sense: sense frequency (motherboard should pull this pin up to appropriate v cc with resistor) 2 pulses per fan revolution figure 23. motherboard power header placement relative to fan power connector and sc242 1.439 1.449 r = 4.75 inches fan power connector location (1.56 inches above motherboard) motherboard fan power header should be positioned within 4.75 inches of fan power connector (lateral distance) slot 1 connector sc242 connector
datasheet 73 intel ? celeron? processor 6.2 ppga package 6.2.1 introduction the intel ? celeron? processor is also offered as an intel boxed processor in the ppga package at the following processor speeds: 500 mhz, 466 mhz, 433 mhz, 400 mhz, 366 mhz, 333 mhz, and 300a mhz. intel boxed processors are intended for system integrators who build systems from motherboards and standard components. the boxed intel celeron processor in the ppga package will be supplied with an unattached fan heat sink. this section documents motherboard and system requirements for the fan heat sink that will be supplied with the boxed intel celeron processor. this section is particularly important for oems that manufacture motherboards for system integrators. unless otherwise noted, all figures in this section are dimensioned in inches. figure 24 shows a mechanical representation of the boxed intel celeron processor in the ppga package. note that the airflow of the fan heat sink is into the center and out of the sides of the fan heat sink. note: the heat sink keepout zones found in this section refer specifically to the boxed processors active- fan heat sink. this does not reflect the worst-case dimensions that may exist with other third party passive or active-fan heat sinks. contact your vendor of choice for their passive or active-fan heat sink dimensions to ensure that mechanical interference with system platform components does not occur. 6.2.2 mechanical specifications this section documents the mechanical specifications of the boxed intel ? celeron? processor fan heat sink. the boxed processor in the ppga package ships with an unattached fan heat sink which has an attached integrated clip. clearance is required around the fan heat sink to ensure unimpeded airflow for proper cooling. the space requirements and dimensions for the boxed processor with integrated fan heat sink are shown in figure 25 and figure 26 . all dimensions are in inches. figure 24. boxed intel ? celeron? processor in ppga package 2d
74 datasheet intel ? celeron? processor figure 25. side view space requirements for the boxed processor figure 26. top view space requirements for the boxed processor 0.34" plastic pin grid array package attached fan power cable fan heatsink 1.22" 0.34" 1.76" fan heatsink fan heatsink for 466C500 mhz mhz processor fan heatsink for 300aC433 mhz processor 370-pin socket attached fan power cable 2.00 2.52
datasheet 75 intel ? celeron? processor 6.2.2.1 boxed processor heat sink dimensions notes: 1. drawings reflect only the specifications of the intel boxed processor product. these dimensions should not be used as a universal keepout zone that covers all heat sinks. it is the system designers responsibility to consider their own proprietary solution when designing the desired keepout zone in their system platform. please refer to the intel ? celeron? processor (ppga) at 466 mhz thermal solution guidelines (order number 245156) for further guidance. 2. specifically applies to the 300aC433 mhz heat sink. 3. specifically applies to the 466C500 mhz heat sink. 6.2.2.2 boxed processor heat sink weight the boxed processor heat sink will not weigh more than 180 grams. figure 27. side view airspace requirements for the boxed processor table 40. boxed processor fan heat sink spatial dimensions 1 dimensions (inches) min typ max notes fan heat sink length (see figure 26 )2.52 fan heat sink height from motherboard (see figure 25 )0.34 fan heat sink height (see figure 25 ) 1.22 1.76 2 3 fan heat sink width (see figure 26 )2.00 airflow keepout zones from end of fan heat sink 0.20 airflow keepout zones from face of fan heat sink 0.20 measure ambient temperature 0.3" above center of fan inlet 0.20 min air space 0.20 min air space fan heatsink processor 1d
76 datasheet intel ? celeron? processor 6.2.2.3 boxed processor thermal cooling solution clip the boxed processor thermal solution requires installation by a system integrator to secure the thermal cooling solution to the processor after it is installed in the 370-pin socket zif socket. motherboards designed for use by system integrators should take care to consider the implications of clip installation and potential scraping of the motherboard pcb underneath the 370-pin socket attach tabs. motherboard components should not be placed too close to the 370-pin socket attach tabs in a way that interferes with the installation of the boxed processor thermal cooling solution (see figure 30 for specification). 6.2.3 boxed processor requirements the boxed processor's fan heat sink requires a +12 v power supply. a fan power cable is attached to the fan and will draw power from a power header on the motherboard. the power cable connector and pin-out are shown in figure 28 . motherboards must provide a matched power header to support the boxed processor. table 41 contains specifications for the input and output signals at the fan heat sink connector. the cable length is 7.0 inches ( 0.25"). the power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. the power header identification and location should be documented in the motherboard documentation or on the motherboard. figure 29 shows the recommended location of the fan power connector relative to the 370-pin socket. the motherboard power header should be positioned within 4.00 inches from the center of the 370-pin socket. figure 28. boxed processor fan heat sink power cable connector description table 41. fan heat sink power and signal specifications description min typ max +12 v: 12 volt fan power supply 7 v 12 v 13.8 v ic: fan current draw 100 ma pin signal straight square pin, 3-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pin pitch, 0.025" square pin width. waldom/molex p/n 22-01-3037 or equivalent. match with straight pin, friction lock header on motherboard waldom/molex p/n 22-23-2031, amp p/n 640456-3, or equivalent. 1 2 3 gnd +12v n/a 123
datasheet 77 intel ? celeron? processor figure 29. motherboard power header placement relative to the intel ? celeron? processor in the ppga package figure 30. top view of motherboard keepout requirements pga370 r = 4.00" 0.14" pga370 0.20" 0.04" 0.04" 0.14" 0.20" 0.30"
78 datasheet intel ? celeron? processor 6.2.4 thermal specifications this section describes the cooling requirements of the fan heat sink solution utilized by the boxed processor. 6.2.4.1 boxed processor cooling requirements the boxed intel ? celeron? processor fan heat sink is designed to keep the processor within thermal specifications under the following conditions: the temperature entering the fan inlet remains below 45c (see figure 27 for measurement location), the provided airflow through the fan heat sink is unimpeded (see figure 27 ), the processor power is generated by commercially available software (applications and operating system) rather than synthetic testing hardware (silicon testers) refer to section 4.0 for intel ? celeron? processor thermal and power specifications. airspace is required around the fan to ensure that the airflow through the fan heat sink is not blocked. blocking the airflow to the fan heat sink reduces the cooling efficiency and decreases fan life. figure 27 illustrates an acceptable airspace clearance for the fan heat sink. figure 31. side view of motherboard keepout requirements fan heatsink 0.34" 0.20" 0.30" 0.04" processor
datasheet 79 intel ? celeron? processor 7.0 intel ? celeron? processor signal description table 42 provides an alphabetical listing of all intel ? celeron? processor signals. the tables at the end of this section summarize the signals by direction: output, input, and i/o. note: unless otherwise noted, the signals apply to both s.e.p. and ppga packages table 42. alphabetical signal reference (sheet 1 of 6) signal type description a[31:3]# i/o the a[31:3]# (address) signals define a 2 32 -byte physical memory address space. when ads# is active, these pins transmit the address of a transaction; when ads# is inactive, these pins transmit transaction type information. these signals must connect the appropriate pins of all agents on the intel ? celeron? processor system bus. the a[31:24]# signals are parity-protected by the ap1# parity signal, and the a[23:3]# signals are parity-protected by the ap0# parity signal. on the active-to-inactive transition of reset#, the processors sample the a[31:3]# pins to determine their power-on configuration. see the pentium ? ii processor developers manual (order number 243502) for details. a20m# i if the a20m# (address-20 mask) input signal is asserted, the intel celeron processor masks physical address bit 20 (a20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. asserting a20m# emulates the 8086 processor's address wrap-around at the 1 mb boundary. assertion of a20m# is only supported in real mode. a20m# is an asynchronous signal. however, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corresponding i/o write bus transaction. ads# i/o the ads# (address strobe) signal is asserted to indicate the validity of the transaction address on the a[31:3]# pins. all bus agents observe the ads# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply id match operations associated with the new transaction. this signal must connect the appropriate pins on all intel celeron processor system bus agents. bclk i the bclk (bus clock) signal determines the bus frequency. all intel celeron processor system bus agents must receive this signal to drive their outputs and latch their inputs on the bclk rising edge. all external timing parameters are specified with respect to the bclk signal. bnr# i/o the bnr# (block next request) signal is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. during a bus stall, the current bus owner cannot issue any new transactions. since multiple agents might need to request a bus stall at the same time, bnr# is a wire-or signal which must connect the appropriate pins of all intel celeron processor system bus agents. in order to avoid wire-or glitches associated with simultaneous edge transitions driven by multiple drivers, bnr# is activated on specific clock edges and sampled on specific clock edges. bp[3:2]# i/o the bp[3:2]# (breakpoint) signals are outputs from the processor that indicate the status of breakpoints. bpm[1:0]# i/o the bpm[1:0]# (breakpoint monitor) signals are breakpoint and performance monitor signals. they are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. bpri# i the bpri# (bus priority request) signal is used to arbitrate for ownership of the intel celeron processor system bus. it must connect the appropriate pins of all intel celeron processor system bus agents. observing bpri# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed, then releases the bus by deasserting bpri#.
80 datasheet intel ? celeron? processor bsel i/o this signal indicates the system bus frequency supported by the processor. a logic low indicates a host bus frequency of 66 mhz. br0# i/o the br0# (bus request) pin drives the breq[0]# signal in the system. during power-up configuration, the central agent asserts the breq0# bus signal in the system to assign the symmetric agent id to the processor. the processor samples its br0# pin on the active-to-inactive transition of reset# to obtain its symmetric agent id. the processor asserts br0# to request the system bus. cpupres# (ppga only) o the cpupres# signal provides the ability for a system board to detect the presence of a processor. this pin is a ground on the processor indicating to the system that a processor is installed. d[63:0]# i/o the d[63:0]# (data) signals are the data signals. these signals provide a 64-bit data path between the intel celeron processor system bus agents, and must connect the appropriate pins on all such agents. the data driver asserts drdy# to indicate a valid data transfer. dbsy# i/o the dbsy# (data bus busy) signal is asserted by the agent responsible for driving data on the intel celeron processor system bus to indicate that the data bus is in use. the data bus is released after dbsy# is deasserted. this signal must connect the appropriate pins on all intel celeron processor system bus agents. defer# i the defer# signal is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. assertion of defer# is normally the responsibility of the addressed memory or i/o agent. this signal must connect the appropriate pins of all intel celeron processor system bus agents. drdy# i/o the drdy# (data ready) signal is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multicycle data transfer, drdy# may be deasserted to insert idle clocks. this signal must connect the appropriate pins of all intel celeron processor system bus agents. edgctrl i the edgctrl input provides agtl+ edge control and should be pulled up to v cc core with a 51 w 5% resistor. emi (s.e.p.p. only) i emi pins should be connected to motherboard ground and/or to chassis ground through zero ohm (0 w ) resistors. the zero ohm resistors should be placed in close proximity to the intel celeron processor connector. the path to chassis ground should be short in length and have a low impedance. these pins are used for emi management purposes. ferr# o the ferr# (floating-point error) signal is asserted when the processor detects an unmasked floating-point error. ferr# is similar to the error# signal on the intel 387 coprocessor, and is included for compatibility with systems using ms- dos*-type floating-point error reporting. flush# i when the flush# input signal is asserted, the processor writes back all data in the modified state from the internal cache and invalidates all internal cache lines. at the completion of this operation, the processor issues a flush acknowledge transaction. the processor does not cache any new data while the flush# signal remains asserted. flush# is an asynchronous signal. however, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corresponding i/o write bus transaction. on the active-to-inactive transition of reset#, the processor samples flush# to determine its power-on configuration. see pentium ? pro family developers manual, volume 1: specifications (order number 242690) for details. hit#, hitm# i/o the hit# (snoop hit) and hitm# (hit modified) signals convey transaction snoop operation results, and must connect the appropriate pins of all intel celeron processor system bus agents. any such agent may assert both hit# and hitm# together to indicate that it requires a snoop stall, which can be continued by reasserting hit# and hitm# together. table 42. alphabetical signal reference (sheet 2 of 6) signal type description
datasheet 81 intel ? celeron? processor ierr# o the ierr# (internal error) signal is asserted by a processor as the result of an internal error. assertion of ierr# is usually accompanied by a shutdown transaction on the intel celeron processor system bus. this transaction may optionally be converted to an external error signal (e.g., nmi) by system core logic. the processor will keep ierr# asserted until the assertion of reset#, binit#, or init#. ignne# i the ignne# (ignore numeric error) signal is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. if ignne# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. ignne# has no effect when the ne bit in control register 0 is set. ignne# is an asynchronous signal. however, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corresponding i/o write bus transaction. init# i the init# (initialization) signal, when asserted, resets integer registers inside all processors without affecting their internal (l1) caches or floating-point registers. each processor then begins execution at the power-on reset vector configured during power-on configuration. the processor continues to handle snoop requests during init# assertion. init# is an asynchronous signal and must connect the appropriate pins of all bus agents. if init# is sampled active on the active to inactive transition of reset#, then the processor executes its built-in self-test (bist). lint[1:0] i the lint[1:0] (local apic interrupt) signals must connect the appropriate pins of all apic bus agents, including all processors and the core logic or i/o apic component. when the apic is disabled, the lint0 signal becomes intr, a maskable interrupt request signal, and lint1 becomes nmi, a nonmaskable interrupt. intr and nmi are backward compatible with the signals of those names on the pentium ? processor. both signals are asynchronous. both of these signals must be software configured via bios programming of the apic register space to be used either as nmi/intr or lint[1:0]. because the apic is enabled by default after reset, operation of these pins as lint[1:0] is the default configuration. lock# i/o the lock# signal indicates to the system that a transaction must occur atomically. this signal must connect the appropriate pins of all system bus agents. for a locked sequence of transactions, lock# is asserted from the beginning of the first transaction end of the last transaction. when the priority agent asserts bpri# to arbitrate for ownership of the system bus, it will wait until it observes lock# deasserted. this enables symmetric agents to retain ownership of the system bus throughout the bus locked operation and ensure the atomicity of lock. picclk i the picclk (apic clock) signal is an input clock to the processor and core logic or i/o apic which is required for operation of all processors, core logic, and i/o apic components on the apic bus. picd[1:0] i/o the picd[1:0] (apic data) signals are used for bidirectional serial message passing on the apic bus, and must connect the appropriate pins of the intel celeron processor for proper initialization. pll1, pll2 (ppga only) i all intel celeron processors have internal analog pll clock generators that require quiet power supplies. pll1 and pll2 are inputs to the internal pll and should be connected to v cc core through a low-pass filter that minimizes jitter. prdy# o the prdy (probe ready) signal is a processor output used by debug tools to determine processor debug readiness. preq# i the preq# (probe request) signal is used by debug tools to request debug operation of the processors. table 42. alphabetical signal reference (sheet 3 of 6) signal type description
82 datasheet intel ? celeron? processor pwrgood i the pwrgood (power good) signal is a 2.5 v tolerant processor input. the processor requires this signal to be a clean indication that the clocks and power supplies (v cc core , etc.) are stable and within their specifications. clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. the signal must then transition monotonically to a high (2.5 v) state. figure 23 illustrates the relationship of pwrgood to other system signals. pwrgood can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of pwrgood. it must also meet the minimum pulse width specification in table 14 and table 15 , and be followed by a 1 ms reset# pulse. the pwrgood signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. it should be driven high throughout boundary scan operation. pwrgood relationship at power-on req[4:0]# i/o the req[4:0]# (request command) signals must connect the appropriate pins of all processor system bus agents. they are asserted by the current bus owner over two clock cycles to define the currently active transaction type. reset# i asserting the reset# signal resets the processor to a known state and invalidates the l1 cache without writing back any of the contents. reset# must stay active for at least one millisecond after v cc core and clk have reached their proper specifications. on observing active reset#, all system bus agents will deassert their outputs within two clocks. a number of bus signals are sampled at the active-to-inactive transition of reset# for power-on configuration. these configuration options are described in the pentium ? pro family developers manual, volume 1: specifications (order number 242690). the processor may have its outputs tristated via power-on configuration. otherwise, if init# is sampled active during the active-to-inactive transition of reset#, the processor will execute its built-in self-test (bist). whether or not bist is executed, the processor will begin program execution at the power on reset vector (default 0_ffff_fff0h). reset# must connect the appropriate pins of all processor system bus agents. rs[2:0]# i the rs[2:0]# (response status) signals are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor system bus agents. table 42. alphabetical signal reference (sheet 4 of 6) signal type description bclk pwrgood reset# 1 ms vcc core , v ref
datasheet 83 intel ? celeron? processor slotocc# (s.e.p.p. only) o slotocc# is defined to allow a system design to detect the presence of a terminator card or processor in a sc242 connector. this pin is not a signal; rather, it is a short to vss. combined with the vid combination of vid[4:0]= 11111 (see section 2.5 ), a system can determine if a sc242 connector is occupied, and whether a processor core is present. the states and values for determining the type of cartridge in the sc242 connector is shown below. slp# i the slp# (sleep) signal, when asserted in stop-grant state, causes processors to enter the sleep state. during sleep state, the processor stops providing internal clock signals to all units, leaving only the phase-locked loop (pll) still operating. processors in this state will not recognize snoops or interrupts. the processor will recognize only assertions of the slp#, stpclk#, and reset# signals while in sleep state. if slp# is deasserted, the processor exits sleep state and returns to stop-grant state, restarting its internal clock signals to the bus and apic processor core units. smi# i the smi# (system management interrupt) signal is asserted asynchronously by system logic. on accepting a system management interrupt, processors save the current state and enter system management mode (smm). an smi acknowledge transaction is issued, and the processor begins program execution from the smm handler. stpclk# i the stpclk# (stop clock) signal, when asserted, causes processors to enter a low power stop-grant state. the processor issues a stop-grant acknowledge transaction, and stops providing internal clock signals to all processor core units except the bus and apic units. the processor continues to snoop bus transactions and may latch interrupts while in stop-grant state. when stpclk# is deasserted, the processor restarts its internal clock to all units, resumes execution, and services any pending interrupt. the assertion of stpclk# has no effect on the bus clock; stpclk# is an asynchronous input. tck i the tck (test clock) signal provides the clock input for the intel celeron processor test access port. tdi i the tdi (test data in) signal transfers serial test data into the processor. tdi provides the serial input needed for jtag specification support. tdo o the tdo (test data out) signal transfers serial test data out of the processor. tdo provides the serial output needed for jtag specification support. testhi (s.e.p.p. only) i refer to section 2.6 for implementation details. thermdn o thermal diode p-n junction. used to calculate core temperature. see section 4.1 . thermdp i thermal diode p-n junction. used to calculate core temperature. see section 4.1 . thermtrip# o the processor protects itself from catastrophic overheating by use of an internal thermal sensor. this sensor is set well above the normal operating temperature to ensure that there are no false trips. the processor will stop all execution when the junction temperature exceeds approximately 135 c. this is signaled to the system by the thermtrip# (thermal trip) pin. once activated, the signal remains latched, and the processor stopped, until reset# goes active. there is no hysteresis built into the thermal sensor itself; as long as the die temperature drops below the trip level, a reset# pulse will reset the processor and execution will continue. if the temperature has not dropped below the trip level, the processor will reassert thermtrip# and remain stopped. table 42. alphabetical signal reference (sheet 5 of 6) signal type description sc242 occupation truth table signal value status slotocc# vid[4:0] 0 anything other than 11111 processor with core in sc242 connector. slotocc# vid[4:0] 0 11111 terminator cartridge in sc242 connector (i.e., no core present). slotocc# vid[4:0] 1 any value sc242 connector not occupied.
84 datasheet intel ? celeron? processor tms i the tms (test mode select) signal is a jtag specification support signal used by debug tools. trdy# i the trdy# (target ready) signal is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. trdy# must connect the appropriate pins of all system bus agents. trst# i the trst# (test reset) signal resets the test access port (tap) logic. intel celeron processors require this signal to be driven low during power on reset. a 680 ohm resistor is the suggested value for a pull down resistor on trst#. v cc 1.5 (ppga only) i the v cc cmos pin provides the cmos voltage for use by the platform. the 2.5 v must be provided to the v cc 2.5 input and 1.5 v must be provided to the v cc 1.5 input. the processor re-routes the 2.5 v input to the v cc cmos output via the package. future processors requiring 1.5 v cmos voltage levels will route the 1.5 v at the v cc 1.5 input to the v cc cmos output. v cc 2.5 (ppga only) i the v cc cmos pin provides the cmos voltage for use by the platform. the 2.5 v must be provided to the v cc 2.5 input and 1.5 v must be provided to the v cc 1.5 input. the processor re-routes the 2.5 v input to the v cc cmos output via the package. future processors requiring 1.5 v cmos voltage levels will route the 1.5 v at the v cc 1.5 input to the v cc cmos output. v cc cmos (ppga only) o the v cc cmos pin provides the cmos voltage for use by the platform. the 2.5 v must be provided to the v cc 2.5 input and 1.5 v must be provided to the v cc 1.5 input. the processor re-routes the 2.5 v input to the v cc cmos output via the package. future processors requiring 1.5 v cmos voltage levels will route the 1.5 v at the v cc 1.5 input to the v cc cmos output. v core det (ppga only) o the v core det signal will float for 2.0 v core processors and will be grounded for future processors with a lower core voltage. vid[4:0] (s.e.p.p.) vid[3:0] (ppga) o the vid (voltage id) pins can be used to support automatic selection of power supply voltages. these pins are not signals, but are either an open circuit or a short circuit to vss on the processor. the combination of opens and shorts defines the voltage required by the processor. the vid pins are needed to cleanly support voltage specification variations on intel celeron processors. see ta b l e 1 for definitions of these pins. the power supply must supply the voltage that is requested by these pins, or disable itself. v ref [7:0] (ppga only) i these input signals are used by the agtl+ inputs as a reference voltage. agtl+ inputs are differential receivers and will use this voltage to determine whether the signal is a logic high or logic low. table 42. alphabetical signal reference (sheet 6 of 6) signal type description
datasheet 85 intel ? celeron? processor 7.1 signal summaries table 43 through table 46 list attributes of the intel ? celeron? processor output, input, and i/o signals. table 43. output signals name active level clock signal group cpupres# (ppga only) low asynch power/other ferr# low asynch cmos output ierr# low asynch cmos output prdy# low bclk agtl+ output slotocc# (s.e.p.p. only) low asynch power/other tdo high tck tap output thermdn n/a asynch power/other thermtrip# low asynch cmos output v core det (ppga only) high asynch power/other vid[4:0] (s.e.p.p.) vid[3:0] (ppga) high asynch power/other table 44. input signals (sheet 1 of 2) name active level clock signal group qualified a20m# low asynch cmos input always 1 bpri# low bclk agtl+ input always bclk high system bus clock always defer# low bclk agtl+ input always flush# low asynch cmos input always 1 ignne# low asynch cmos input always 1 init# low asynch cmos input always 1 intr high asynch cmos input apic disabled mode lint[1:0] high asynch cmos input apic enabled mode nmi high asynch cmos input apic disabled mode picclk high apic clock always preq# low asynch cmos input always pwrgood high asynch cmos input always reset# low bclk agtl+ input always rs[2:0]# low bclk agtl+ input always slp# low asynch cmos input during stop-grant state smi# low asynch cmos input stpclk# low asynch cmos input tck high tap input
86 datasheet intel ? celeron? processor note: 1. synchronous assertion with active trdy# ensures synchronization. tdi high tck tap input testhi (s.e.p.p. only) high asynch power/other always thermdp n/a asynch power/other tms high tck tap input trst# low asynch tap input trdy# low bclk agtl+ input table 44. input signals (sheet 2 of 2) name active level clock signal group qualified table 45. input/output signals (single driver) name active level clock signal group qualified bsel low asynch power/other always bp[3:2] low bclk agtl+ i/o always a[31:3]# low bclk agtl+ i/o ads#, ads#+1 ads# low bclk agtl+ i/o always bpm[1:0]# low bclk agtl+ i/o always d[63:0]# low bclk agtl+ i/o drdy# dbsy# low bclk agtl+ i/o always drdy# low bclk agtl+ i/o always lock# low bclk agtl+ i/o always req[4:0]# low bclk agtl+ i/o ads#, ads#+1 table 46. input/output signals (multiple driver) name active level clock signal group qualified bnr# low bclk agtl+ i/o always hit# low bclk agtl+ i/o always hitm# low bclk agtl+ i/o always picd[1:0] high picclk apic i/o always

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